diff options
-rw-r--r-- | riscv/execute.h | 186 | ||||
-rw-r--r-- | riscv/insns/fcvt_d_lu.h (renamed from riscv/insns/fcvtu_d_l.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fcvt_d_wu.h (renamed from riscv/insns/fcvtu_d_w.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fcvt_lu_d.h (renamed from riscv/insns/fcvtu_l_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fcvt_lu_s.h (renamed from riscv/insns/fcvtu_l_s.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fcvt_s_lu.h (renamed from riscv/insns/fcvtu_s_l.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fcvt_s_wu.h (renamed from riscv/insns/fcvtu_s_w.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fcvt_wu_d.h (renamed from riscv/insns/fcvtu_w_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fcvt_wu_s.h (renamed from riscv/insns/fcvtu_w_s.h) | 0 | ||||
-rw-r--r-- | riscv/insns/feq_d.h (renamed from riscv/insns/fc_eq_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/feq_s.h (renamed from riscv/insns/fc_eq_s.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fld.h (renamed from riscv/insns/lf_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fle_d.h (renamed from riscv/insns/fc_le_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fle_s.h (renamed from riscv/insns/fc_le_s.h) | 0 | ||||
-rw-r--r-- | riscv/insns/flt_d.h (renamed from riscv/insns/fc_lt_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/flt_s.h (renamed from riscv/insns/fc_lt_s.h) | 0 | ||||
-rw-r--r-- | riscv/insns/flw.h (renamed from riscv/insns/lf_w.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fsd.h (renamed from riscv/insns/sf_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fsgnj_d.h (renamed from riscv/insns/fsinj_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fsgnj_s.h (renamed from riscv/insns/fsinj_s.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fsgnjn_d.h (renamed from riscv/insns/fsinjn_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fsgnjn_s.h (renamed from riscv/insns/fsinjn_s.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fsgnjx_d.h (renamed from riscv/insns/fsmul_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fsgnjx_s.h (renamed from riscv/insns/fsmul_s.h) | 0 | ||||
-rw-r--r-- | riscv/insns/fsw.h (renamed from riscv/insns/sf_w.h) | 0 | ||||
-rw-r--r-- | riscv/insns/lb.h (renamed from riscv/insns/l_b.h) | 0 | ||||
-rw-r--r-- | riscv/insns/lbu.h (renamed from riscv/insns/l_bu.h) | 0 | ||||
-rw-r--r-- | riscv/insns/ld.h (renamed from riscv/insns/l_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/lh.h (renamed from riscv/insns/l_h.h) | 0 | ||||
-rw-r--r-- | riscv/insns/lhu.h (renamed from riscv/insns/l_hu.h) | 0 | ||||
-rw-r--r-- | riscv/insns/lw.h (renamed from riscv/insns/l_w.h) | 0 | ||||
-rw-r--r-- | riscv/insns/lwu.h (renamed from riscv/insns/l_wu.h) | 0 | ||||
-rw-r--r-- | riscv/insns/mftx_d.h (renamed from riscv/insns/mff_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/mftx_s.h (renamed from riscv/insns/mff_s.h) | 0 | ||||
-rw-r--r-- | riscv/insns/mxtf_d.h (renamed from riscv/insns/mtf_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/mxtf_s.h (renamed from riscv/insns/mtf_s.h) | 0 | ||||
-rw-r--r-- | riscv/insns/sb.h (renamed from riscv/insns/s_b.h) | 0 | ||||
-rw-r--r-- | riscv/insns/sd.h (renamed from riscv/insns/s_d.h) | 0 | ||||
-rw-r--r-- | riscv/insns/sh.h (renamed from riscv/insns/s_h.h) | 0 | ||||
-rw-r--r-- | riscv/insns/sw.h (renamed from riscv/insns/s_w.h) | 0 |
40 files changed, 93 insertions, 93 deletions
diff --git a/riscv/execute.h b/riscv/execute.h index f78375a..ab0fed7 100644 --- a/riscv/execute.h +++ b/riscv/execute.h @@ -27,37 +27,37 @@ switch((insn.bits >> 0x0) & 0x7f) { case 0x0: { - #include "insns/l_b.h" + #include "insns/lb.h" break; } case 0x1: { - #include "insns/l_h.h" + #include "insns/lh.h" break; } case 0x2: { - #include "insns/l_w.h" + #include "insns/lw.h" break; } case 0x3: { - #include "insns/l_d.h" + #include "insns/ld.h" break; } case 0x4: { - #include "insns/l_bu.h" + #include "insns/lbu.h" break; } case 0x5: { - #include "insns/l_hu.h" + #include "insns/lhu.h" break; } case 0x6: { - #include "insns/l_wu.h" + #include "insns/lwu.h" break; } default: @@ -73,12 +73,12 @@ switch((insn.bits >> 0x0) & 0x7f) { case 0x2: { - #include "insns/lf_w.h" + #include "insns/flw.h" break; } case 0x3: { - #include "insns/lf_d.h" + #include "insns/fld.h" break; } default: @@ -244,22 +244,22 @@ switch((insn.bits >> 0x0) & 0x7f) { case 0x0: { - #include "insns/s_b.h" + #include "insns/sb.h" break; } case 0x1: { - #include "insns/s_h.h" + #include "insns/sh.h" break; } case 0x2: { - #include "insns/s_w.h" + #include "insns/sw.h" break; } case 0x3: { - #include "insns/s_d.h" + #include "insns/sd.h" break; } default: @@ -275,12 +275,12 @@ switch((insn.bits >> 0x0) & 0x7f) { case 0x2: { - #include "insns/sf_w.h" + #include "insns/fsw.h" break; } case 0x3: { - #include "insns/sf_d.h" + #include "insns/fsd.h" break; } default: @@ -434,6 +434,11 @@ switch((insn.bits >> 0x0) & 0x7f) { case 0x0: { + if((insn.bits & 0x1ffff) == 0x43b) + { + #include "insns/mulw.h" + break; + } if((insn.bits & 0x1ffff) == 0x3b) { #include "insns/addw.h" @@ -444,11 +449,6 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/subw.h" break; } - if((insn.bits & 0x1ffff) == 0x43b) - { - #include "insns/mulw.h" - break; - } #include "insns/unimp.h" } case 0x1: @@ -588,11 +588,6 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/amomaxu_d.h" break; } - if((insn.bits & 0x1ffff) == 0x11c3) - { - #include "insns/amomin_d.h" - break; - } if((insn.bits & 0x1ffff) == 0x1c3) { #include "insns/amoadd_d.h" @@ -613,6 +608,11 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/amoswap_d.h" break; } + if((insn.bits & 0x1ffff) == 0x11c3) + { + #include "insns/amomin_d.h" + break; + } #include "insns/unimp.h" } default: @@ -691,6 +691,11 @@ switch((insn.bits >> 0x0) & 0x7f) { case 0x0: { + if((insn.bits & 0x3ff1ff) == 0x9053) + { + #include "insns/fcvt_lu_s.h" + break; + } if((insn.bits & 0x3ff1ff) == 0x11053) { #include "insns/fcvt_s_d.h" @@ -706,11 +711,6 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/fcvt_s_w.h" break; } - if((insn.bits & 0x3ff1ff) == 0xb053) - { - #include "insns/fcvtu_w_s.h" - break; - } if((insn.bits & 0x3ff1ff) == 0x8053) { #include "insns/fcvt_l_s.h" @@ -721,11 +721,21 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/fdiv_s.h" break; } + if((insn.bits & 0x3ff1ff) == 0xd053) + { + #include "insns/fcvt_s_lu.h" + break; + } if((insn.bits & 0x1f1ff) == 0x2053) { #include "insns/fmul_s.h" break; } + if((insn.bits & 0x3ff1ff) == 0xb053) + { + #include "insns/fcvt_wu_s.h" + break; + } if((insn.bits & 0x3ff1ff) == 0xa053) { #include "insns/fcvt_w_s.h" @@ -738,17 +748,7 @@ switch((insn.bits >> 0x0) & 0x7f) } if((insn.bits & 0x3ff1ff) == 0xf053) { - #include "insns/fcvtu_s_w.h" - break; - } - if((insn.bits & 0x3ff1ff) == 0xd053) - { - #include "insns/fcvtu_s_l.h" - break; - } - if((insn.bits & 0x3ff1ff) == 0x9053) - { - #include "insns/fcvtu_l_s.h" + #include "insns/fcvt_s_wu.h" break; } if((insn.bits & 0x3ff1ff) == 0xc053) @@ -770,6 +770,11 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/fcvt_d_l.h" break; } + if((insn.bits & 0x3ff1ff) == 0x100d3) + { + #include "insns/fcvt_d_s.h" + break; + } if((insn.bits & 0x3ff1ff) == 0x80d3) { #include "insns/fcvt_l_d.h" @@ -780,14 +785,19 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/fmul_d.h" break; } - if((insn.bits & 0x3ff1ff) == 0xa0d3) + if((insn.bits & 0x3ff1ff) == 0xb0d3) { - #include "insns/fcvt_w_d.h" + #include "insns/fcvt_wu_d.h" break; } - if((insn.bits & 0x3ff1ff) == 0xb0d3) + if((insn.bits & 0x3ff1ff) == 0xd0d3) { - #include "insns/fcvtu_w_d.h" + #include "insns/fcvt_d_lu.h" + break; + } + if((insn.bits & 0x3ff1ff) == 0xa0d3) + { + #include "insns/fcvt_w_d.h" break; } if((insn.bits & 0x1f1ff) == 0xd3) @@ -797,7 +807,7 @@ switch((insn.bits >> 0x0) & 0x7f) } if((insn.bits & 0x3ff1ff) == 0x90d3) { - #include "insns/fcvtu_l_d.h" + #include "insns/fcvt_lu_d.h" break; } if((insn.bits & 0x1f1ff) == 0x10d3) @@ -815,33 +825,23 @@ switch((insn.bits >> 0x0) & 0x7f) #include "insns/fdiv_d.h" break; } - if((insn.bits & 0x3ff1ff) == 0xd0d3) - { - #include "insns/fcvtu_d_l.h" - break; - } #include "insns/unimp.h" } case 0x4: { - if((insn.bits & 0x1ffff) == 0x6e53) + if((insn.bits & 0xf83fffff) == 0x1de53) { - #include "insns/fsinjn_s.h" + #include "insns/mtfsr.h" break; } if((insn.bits & 0x7c1ffff) == 0x18e53) { - #include "insns/mff_s.h" + #include "insns/mftx_s.h" break; } - if((insn.bits & 0xf83fffff) == 0x1de53) - { - #include "insns/mtfsr.h" - break; - } - if((insn.bits & 0x3fffff) == 0x1ce53) + if((insn.bits & 0x1ffff) == 0x17e53) { - #include "insns/mtf_s.h" + #include "insns/fle_s.h" break; } if((insn.bits & 0x7ffffff) == 0x1be53) @@ -851,86 +851,86 @@ switch((insn.bits >> 0x0) & 0x7f) } if((insn.bits & 0x1ffff) == 0x16e53) { - #include "insns/fc_lt_s.h" + #include "insns/flt_s.h" + break; + } + if((insn.bits & 0x1ffff) == 0x15e53) + { + #include "insns/feq_s.h" break; } if((insn.bits & 0x1ffff) == 0x7e53) { - #include "insns/fsmul_s.h" + #include "insns/fsgnjx_s.h" break; } - if((insn.bits & 0x1ffff) == 0x5e53) + if((insn.bits & 0x3fffff) == 0x1ce53) { - #include "insns/fsinj_s.h" + #include "insns/mxtf_s.h" break; } - if((insn.bits & 0x1ffff) == 0x17e53) + if((insn.bits & 0x1ffff) == 0x5e53) { - #include "insns/fc_le_s.h" + #include "insns/fsgnj_s.h" break; } - if((insn.bits & 0x1ffff) == 0x15e53) + if((insn.bits & 0x1ffff) == 0x6e53) { - #include "insns/fc_eq_s.h" + #include "insns/fsgnjn_s.h" break; } #include "insns/unimp.h" } case 0x5: { - if((insn.bits & 0x7c1ffff) == 0x18ed3) + if((insn.bits & 0x3fffff) == 0xeed3) { - #include "insns/mff_d.h" + #include "insns/fcvt_d_w.h" break; } - if((insn.bits & 0x1ffff) == 0x6ed3) + if((insn.bits & 0x7c1ffff) == 0x18ed3) { - #include "insns/fsinjn_d.h" + #include "insns/mftx_d.h" break; } - if((insn.bits & 0x3fffff) == 0xeed3) + if((insn.bits & 0x1ffff) == 0x17ed3) { - #include "insns/fcvt_d_w.h" + #include "insns/fle_d.h" break; } - if((insn.bits & 0x3fffff) == 0x10ed3) + if((insn.bits & 0x1ffff) == 0x16ed3) { - #include "insns/fcvt_d_s.h" + #include "insns/flt_d.h" break; } - if((insn.bits & 0x3fffff) == 0x1ced3) + if((insn.bits & 0x1ffff) == 0x7ed3) { - #include "insns/mtf_d.h" + #include "insns/fsgnjx_d.h" break; } - if((insn.bits & 0x3fffff) == 0xfed3) + if((insn.bits & 0x1ffff) == 0x15ed3) { - #include "insns/fcvtu_d_w.h" + #include "insns/feq_d.h" break; } - if((insn.bits & 0x1ffff) == 0x16ed3) + if((insn.bits & 0x3fffff) == 0xfed3) { - #include "insns/fc_lt_d.h" + #include "insns/fcvt_d_wu.h" break; } - if((insn.bits & 0x1ffff) == 0x15ed3) + if((insn.bits & 0x1ffff) == 0x6ed3) { - #include "insns/fc_eq_d.h" + #include "insns/fsgnjn_d.h" break; } - if((insn.bits & 0x1ffff) == 0x7ed3) + if((insn.bits & 0x3fffff) == 0x1ced3) { - #include "insns/fsmul_d.h" + #include "insns/mxtf_d.h" break; } if((insn.bits & 0x1ffff) == 0x5ed3) { - #include "insns/fsinj_d.h" - break; - } - if((insn.bits & 0x1ffff) == 0x17ed3) - { - #include "insns/fc_le_d.h" + #include "insns/fsgnj_d.h" break; } #include "insns/unimp.h" diff --git a/riscv/insns/fcvtu_d_l.h b/riscv/insns/fcvt_d_lu.h index 68c0482..68c0482 100644 --- a/riscv/insns/fcvtu_d_l.h +++ b/riscv/insns/fcvt_d_lu.h diff --git a/riscv/insns/fcvtu_d_w.h b/riscv/insns/fcvt_d_wu.h index 2757790..2757790 100644 --- a/riscv/insns/fcvtu_d_w.h +++ b/riscv/insns/fcvt_d_wu.h diff --git a/riscv/insns/fcvtu_l_d.h b/riscv/insns/fcvt_lu_d.h index bd460d5..bd460d5 100644 --- a/riscv/insns/fcvtu_l_d.h +++ b/riscv/insns/fcvt_lu_d.h diff --git a/riscv/insns/fcvtu_l_s.h b/riscv/insns/fcvt_lu_s.h index 1ed4594..1ed4594 100644 --- a/riscv/insns/fcvtu_l_s.h +++ b/riscv/insns/fcvt_lu_s.h diff --git a/riscv/insns/fcvtu_s_l.h b/riscv/insns/fcvt_s_lu.h index f149229..f149229 100644 --- a/riscv/insns/fcvtu_s_l.h +++ b/riscv/insns/fcvt_s_lu.h diff --git a/riscv/insns/fcvtu_s_w.h b/riscv/insns/fcvt_s_wu.h index 4c53c01..4c53c01 100644 --- a/riscv/insns/fcvtu_s_w.h +++ b/riscv/insns/fcvt_s_wu.h diff --git a/riscv/insns/fcvtu_w_d.h b/riscv/insns/fcvt_wu_d.h index 93860e8..93860e8 100644 --- a/riscv/insns/fcvtu_w_d.h +++ b/riscv/insns/fcvt_wu_d.h diff --git a/riscv/insns/fcvtu_w_s.h b/riscv/insns/fcvt_wu_s.h index 04b8fb2..04b8fb2 100644 --- a/riscv/insns/fcvtu_w_s.h +++ b/riscv/insns/fcvt_wu_s.h diff --git a/riscv/insns/fc_eq_d.h b/riscv/insns/feq_d.h index 9db8760..9db8760 100644 --- a/riscv/insns/fc_eq_d.h +++ b/riscv/insns/feq_d.h diff --git a/riscv/insns/fc_eq_s.h b/riscv/insns/feq_s.h index 658e8f6..658e8f6 100644 --- a/riscv/insns/fc_eq_s.h +++ b/riscv/insns/feq_s.h diff --git a/riscv/insns/lf_d.h b/riscv/insns/fld.h index 123dea4..123dea4 100644 --- a/riscv/insns/lf_d.h +++ b/riscv/insns/fld.h diff --git a/riscv/insns/fc_le_d.h b/riscv/insns/fle_d.h index da76187..da76187 100644 --- a/riscv/insns/fc_le_d.h +++ b/riscv/insns/fle_d.h diff --git a/riscv/insns/fc_le_s.h b/riscv/insns/fle_s.h index 9c83a17..9c83a17 100644 --- a/riscv/insns/fc_le_s.h +++ b/riscv/insns/fle_s.h diff --git a/riscv/insns/fc_lt_d.h b/riscv/insns/flt_d.h index 01d135a..01d135a 100644 --- a/riscv/insns/fc_lt_d.h +++ b/riscv/insns/flt_d.h diff --git a/riscv/insns/fc_lt_s.h b/riscv/insns/flt_s.h index 52eee5d..52eee5d 100644 --- a/riscv/insns/fc_lt_s.h +++ b/riscv/insns/flt_s.h diff --git a/riscv/insns/lf_w.h b/riscv/insns/flw.h index 335fd7d..335fd7d 100644 --- a/riscv/insns/lf_w.h +++ b/riscv/insns/flw.h diff --git a/riscv/insns/sf_d.h b/riscv/insns/fsd.h index 113398e..113398e 100644 --- a/riscv/insns/sf_d.h +++ b/riscv/insns/fsd.h diff --git a/riscv/insns/fsinj_d.h b/riscv/insns/fsgnj_d.h index f66e804..f66e804 100644 --- a/riscv/insns/fsinj_d.h +++ b/riscv/insns/fsgnj_d.h diff --git a/riscv/insns/fsinj_s.h b/riscv/insns/fsgnj_s.h index 35609ac..35609ac 100644 --- a/riscv/insns/fsinj_s.h +++ b/riscv/insns/fsgnj_s.h diff --git a/riscv/insns/fsinjn_d.h b/riscv/insns/fsgnjn_d.h index 22de215..22de215 100644 --- a/riscv/insns/fsinjn_d.h +++ b/riscv/insns/fsgnjn_d.h diff --git a/riscv/insns/fsinjn_s.h b/riscv/insns/fsgnjn_s.h index dd66d71..dd66d71 100644 --- a/riscv/insns/fsinjn_s.h +++ b/riscv/insns/fsgnjn_s.h diff --git a/riscv/insns/fsmul_d.h b/riscv/insns/fsgnjx_d.h index 331b6e4..331b6e4 100644 --- a/riscv/insns/fsmul_d.h +++ b/riscv/insns/fsgnjx_d.h diff --git a/riscv/insns/fsmul_s.h b/riscv/insns/fsgnjx_s.h index b455406..b455406 100644 --- a/riscv/insns/fsmul_s.h +++ b/riscv/insns/fsgnjx_s.h diff --git a/riscv/insns/sf_w.h b/riscv/insns/fsw.h index 23d3333..23d3333 100644 --- a/riscv/insns/sf_w.h +++ b/riscv/insns/fsw.h diff --git a/riscv/insns/l_b.h b/riscv/insns/lb.h index 81ba7de..81ba7de 100644 --- a/riscv/insns/l_b.h +++ b/riscv/insns/lb.h diff --git a/riscv/insns/l_bu.h b/riscv/insns/lbu.h index 12c688a..12c688a 100644 --- a/riscv/insns/l_bu.h +++ b/riscv/insns/lbu.h diff --git a/riscv/insns/l_d.h b/riscv/insns/ld.h index 940d348..940d348 100644 --- a/riscv/insns/l_d.h +++ b/riscv/insns/ld.h diff --git a/riscv/insns/l_h.h b/riscv/insns/lh.h index ec25bc4..ec25bc4 100644 --- a/riscv/insns/l_h.h +++ b/riscv/insns/lh.h diff --git a/riscv/insns/l_hu.h b/riscv/insns/lhu.h index 0999c00..0999c00 100644 --- a/riscv/insns/l_hu.h +++ b/riscv/insns/lhu.h diff --git a/riscv/insns/l_w.h b/riscv/insns/lw.h index 769c9fd..769c9fd 100644 --- a/riscv/insns/l_w.h +++ b/riscv/insns/lw.h diff --git a/riscv/insns/l_wu.h b/riscv/insns/lwu.h index 5e62b0f..5e62b0f 100644 --- a/riscv/insns/l_wu.h +++ b/riscv/insns/lwu.h diff --git a/riscv/insns/mff_d.h b/riscv/insns/mftx_d.h index 31be4cb..31be4cb 100644 --- a/riscv/insns/mff_d.h +++ b/riscv/insns/mftx_d.h diff --git a/riscv/insns/mff_s.h b/riscv/insns/mftx_s.h index 589b33b..589b33b 100644 --- a/riscv/insns/mff_s.h +++ b/riscv/insns/mftx_s.h diff --git a/riscv/insns/mtf_d.h b/riscv/insns/mxtf_d.h index 29792ec..29792ec 100644 --- a/riscv/insns/mtf_d.h +++ b/riscv/insns/mxtf_d.h diff --git a/riscv/insns/mtf_s.h b/riscv/insns/mxtf_s.h index 54546ea..54546ea 100644 --- a/riscv/insns/mtf_s.h +++ b/riscv/insns/mxtf_s.h diff --git a/riscv/insns/s_b.h b/riscv/insns/sb.h index af5bd10..af5bd10 100644 --- a/riscv/insns/s_b.h +++ b/riscv/insns/sb.h diff --git a/riscv/insns/s_d.h b/riscv/insns/sd.h index 2009149..2009149 100644 --- a/riscv/insns/s_d.h +++ b/riscv/insns/sd.h diff --git a/riscv/insns/s_h.h b/riscv/insns/sh.h index a484e1e..a484e1e 100644 --- a/riscv/insns/s_h.h +++ b/riscv/insns/sh.h diff --git a/riscv/insns/s_w.h b/riscv/insns/sw.h index dbe260f..dbe260f 100644 --- a/riscv/insns/s_w.h +++ b/riscv/insns/sw.h |