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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-08-16 22:01:29 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-08-27 21:03:47 -0700 |
commit | bfc2bead78ce8237aa48f403808f1699b9190862 (patch) | |
tree | 98402f080a159fdc20b28ebb00bfa09e077d20ed /riscv | |
parent | 5f76a0d1fa68bb80560cb890405c42041f744e89 (diff) | |
download | riscv-isa-sim-bfc2bead78ce8237aa48f403808f1699b9190862.zip riscv-isa-sim-bfc2bead78ce8237aa48f403808f1699b9190862.tar.gz riscv-isa-sim-bfc2bead78ce8237aa48f403808f1699b9190862.tar.bz2 |
rvv: remove quad instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/encoding.h | 12 | ||||
-rw-r--r-- | riscv/insns/vqmacc_vv.h | 5 | ||||
-rw-r--r-- | riscv/insns/vqmacc_vx.h | 5 | ||||
-rw-r--r-- | riscv/insns/vqmaccsu_vv.h | 5 | ||||
-rw-r--r-- | riscv/insns/vqmaccsu_vx.h | 5 | ||||
-rw-r--r-- | riscv/insns/vqmaccu_vv.h | 5 | ||||
-rw-r--r-- | riscv/insns/vqmaccu_vx.h | 5 | ||||
-rw-r--r-- | riscv/insns/vqmaccus_vx.h | 5 | ||||
-rw-r--r-- | riscv/processor.cc | 5 | ||||
-rw-r--r-- | riscv/processor.h | 1 | ||||
-rw-r--r-- | riscv/riscv.mk.in | 7 |
11 files changed, 0 insertions, 60 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index bc7dc87..380b660 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1414,14 +1414,6 @@ #define MASK_VNCLIPU_WX 0xfc00707f #define MATCH_VNCLIP_WX 0xbc004057 #define MASK_VNCLIP_WX 0xfc00707f -#define MATCH_VQMACCU_VX 0xf0004057 -#define MASK_VQMACCU_VX 0xfc00707f -#define MATCH_VQMACC_VX 0xf4004057 -#define MASK_VQMACC_VX 0xfc00707f -#define MATCH_VQMACCUS_VX 0xf8004057 -#define MASK_VQMACCUS_VX 0xfc00707f -#define MATCH_VQMACCSU_VX 0xfc004057 -#define MASK_VQMACCSU_VX 0xfc00707f #define MATCH_VADD_VV 0x57 #define MASK_VADD_VV 0xfc00707f #define MATCH_VSUB_VV 0x8000057 @@ -2710,10 +2702,6 @@ DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX) DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX) DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX) DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX) -DECLARE_INSN(vqmaccu_vx, MATCH_VQMACCU_VX, MASK_VQMACCU_VX) -DECLARE_INSN(vqmacc_vx, MATCH_VQMACC_VX, MASK_VQMACC_VX) -DECLARE_INSN(vqmaccus_vx, MATCH_VQMACCUS_VX, MASK_VQMACCUS_VX) -DECLARE_INSN(vqmaccsu_vx, MATCH_VQMACCSU_VX, MASK_VQMACCSU_VX) DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV) DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV) DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV) diff --git a/riscv/insns/vqmacc_vv.h b/riscv/insns/vqmacc_vv.h deleted file mode 100644 index 3557b25..0000000 --- a/riscv/insns/vqmacc_vv.h +++ /dev/null @@ -1,5 +0,0 @@ -// vqsmacc.vv vd, vs2, vs1 -VI_VV_LOOP_QUAD -({ - VI_QUAD_OP_AND_ASSIGN(vs2, vs1, vd_w, *, +, int); -}) diff --git a/riscv/insns/vqmacc_vx.h b/riscv/insns/vqmacc_vx.h deleted file mode 100644 index 83fd544..0000000 --- a/riscv/insns/vqmacc_vx.h +++ /dev/null @@ -1,5 +0,0 @@ -// vqmacc.vx vd, vs2, rs1 -VI_VX_LOOP_QUAD -({ - VI_QUAD_OP_AND_ASSIGN(vs2, rs1, vd_w, *, +, int); -}) diff --git a/riscv/insns/vqmaccsu_vv.h b/riscv/insns/vqmaccsu_vv.h deleted file mode 100644 index 41bf9ad..0000000 --- a/riscv/insns/vqmaccsu_vv.h +++ /dev/null @@ -1,5 +0,0 @@ -// vqmaccsu.vx vd, vs2, rs1 -VI_VV_LOOP_QUAD -({ - VI_QUAD_OP_AND_ASSIGN_MIX(vs2, vs1, vd_w, *, +, int, uint, int); -}) diff --git a/riscv/insns/vqmaccsu_vx.h b/riscv/insns/vqmaccsu_vx.h deleted file mode 100644 index 147d2ee..0000000 --- a/riscv/insns/vqmaccsu_vx.h +++ /dev/null @@ -1,5 +0,0 @@ -// vqmaccsu.vx vd, vs2, rs1 -VI_VX_LOOP_QUAD -({ - VI_QUAD_OP_AND_ASSIGN_MIX(vs2, rs1, vd_w, *, +, int, uint, int); -}) diff --git a/riscv/insns/vqmaccu_vv.h b/riscv/insns/vqmaccu_vv.h deleted file mode 100644 index d4559b1..0000000 --- a/riscv/insns/vqmaccu_vv.h +++ /dev/null @@ -1,5 +0,0 @@ -// vqmaccu.vv vd, vs2, vs1 -VI_VV_LOOP_QUAD -({ - VI_QUAD_OP_AND_ASSIGN(vs2, vs1, vd_w, *, +, uint); -}) diff --git a/riscv/insns/vqmaccu_vx.h b/riscv/insns/vqmaccu_vx.h deleted file mode 100644 index b8a3484..0000000 --- a/riscv/insns/vqmaccu_vx.h +++ /dev/null @@ -1,5 +0,0 @@ -// vqmaccu.vx vd, vs2, rs1 -VI_VX_LOOP_QUAD -({ - VI_QUAD_OP_AND_ASSIGN(vs2, rs1, vd_w, *, +, uint); -}) diff --git a/riscv/insns/vqmaccus_vx.h b/riscv/insns/vqmaccus_vx.h deleted file mode 100644 index 59ea589..0000000 --- a/riscv/insns/vqmaccus_vx.h +++ /dev/null @@ -1,5 +0,0 @@ -// vqmaccus.vx vd, vs2, rs1 -VI_VX_LOOP_QUAD -({ - VI_QUAD_OP_AND_ASSIGN_MIX(vs2, rs1, vd_w, *, +, int, int, uint); -}) diff --git a/riscv/processor.cc b/riscv/processor.cc index d309f94..15d8f8e 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -264,8 +264,6 @@ void processor_t::parse_isa_string(const char* str) auto ext_str = std::string(ext, end - ext); if (ext_str == "zfh") { extension_table[EXT_ZFH] = true; - } else if (ext_str == "zvqmac") { - extension_table[EXT_ZVQMAC] = true; } else { sprintf(error_msg, "unsupported extension '%s'", ext_str.c_str()); bad_isa_string(str, error_msg); @@ -291,9 +289,6 @@ void processor_t::parse_isa_string(const char* str) if (supports_extension('Q') && !supports_extension('D')) bad_isa_string(str, "'Q' extension requires 'D'"); - - if (supports_extension(EXT_ZVQMAC) && !supports_extension('V')) - bad_isa_string(str, "'Zvqmac' extension requires 'V'"); } void state_t::reset(reg_t max_isa) diff --git a/riscv/processor.h b/riscv/processor.h index 5d7baeb..3575a5d 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -247,7 +247,6 @@ typedef enum { // 65('A') ~ 90('Z') is reserved for standard isa in misa EXT_ZFH = 0, EXT_ZVEDIV, - EXT_ZVQMAC, } isa_extension_t; // Count number of contiguous 1 bits starting from the LSB. diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 6a86158..da50b94 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -450,13 +450,6 @@ riscv_insn_ext_v_alu_int = \ vor_vi \ vor_vv \ vor_vx \ - vqmacc_vv \ - vqmacc_vx \ - vqmaccsu_vv \ - vqmaccsu_vx \ - vqmaccu_vv \ - vqmaccu_vx \ - vqmaccus_vx \ vredand_vs \ vredmax_vs \ vredmaxu_vs \ |