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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-09-22 21:02:15 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-09-23 01:35:58 -0700 |
| commit | 0c60f1008b8aa665e29e100d0e80c8aa9b79efae (patch) | |
| tree | 97adb4d42a4932e2f836d32252d28415eb09a38d /riscv | |
| parent | b8832af2d97f1936c8b813628c2941d22719d736 (diff) | |
| download | riscv-isa-sim-0c60f1008b8aa665e29e100d0e80c8aa9b79efae.zip riscv-isa-sim-0c60f1008b8aa665e29e100d0e80c8aa9b79efae.tar.gz riscv-isa-sim-0c60f1008b8aa665e29e100d0e80c8aa9b79efae.tar.bz2 | |
rvv: commitlog: add peek parameter to get_csr
commitlog needs to read all affected csrs but some of them may violate the
permisson.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/processor.cc | 6 | ||||
| -rw-r--r-- | riscv/processor.h | 4 |
2 files changed, 7 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 00e91f9..05bfe87 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -1299,7 +1299,7 @@ void processor_t::set_csr(int which, reg_t val) // Note that get_csr is sometimes called when read side-effects should not // be actioned. In other words, Spike cannot currently support CSRs with // side effects on reads. -reg_t processor_t::get_csr(int which, insn_t insn, bool write) +reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek) { uint32_t ctr_en = -1; if (state.prv < PRV_M) @@ -1643,6 +1643,10 @@ out: // Check permissions. Raise virtual-instruction exception if V=1, // privileges are insufficient, and the CSR belongs to supervisor or // hypervisor. Raise illegal-instruction exception otherwise. + + if (peek) + return res; + unsigned csr_priv = get_field(which, 0x300); bool csr_read_only = get_field(which, 0xC00) == 3; unsigned priv = state.prv == PRV_S && !state.v ? PRV_HS : state.prv; diff --git a/riscv/processor.h b/riscv/processor.h index 14ba843..169b43f 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -272,8 +272,8 @@ public: void reset(); void step(size_t n); // run for n cycles void set_csr(int which, reg_t val); - reg_t get_csr(int which, insn_t insn, bool write); - reg_t get_csr(int which) { return get_csr(which, insn_t(0), false); } + reg_t get_csr(int which, insn_t insn, bool write, bool peek = 0); + reg_t get_csr(int which) { return get_csr(which, insn_t(0), false, true); } mmu_t* get_mmu() { return mmu; } state_t* get_state() { return &state; } unsigned get_xlen() { return xlen; } |