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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-16 10:42:08 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-21 14:12:53 +0800 |
| commit | 04154f2b305c222674c8cecf692b1b63edc8c6cb (patch) | |
| tree | 4fbda5e7782df92304b5ffc35c44ef64bb93731e /riscv | |
| parent | 72df59bec2b2eaa3438a41b33df608571048d6ed (diff) | |
| download | riscv-isa-sim-04154f2b305c222674c8cecf692b1b63edc8c6cb.zip riscv-isa-sim-04154f2b305c222674c8cecf692b1b63edc8c6cb.tar.gz riscv-isa-sim-04154f2b305c222674c8cecf692b1b63edc8c6cb.tar.bz2 | |
Update fields name for sreg1/sreg2
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/decode.h | 4 | ||||
| -rw-r--r-- | riscv/decode_macros.h | 4 | ||||
| -rw-r--r-- | riscv/insns/cm_mva01s.h | 6 | ||||
| -rw-r--r-- | riscv/insns/cm_mvsa01.h | 6 |
4 files changed, 10 insertions, 10 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index d27f682..a55b069 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -121,8 +121,8 @@ public: uint64_t rvc_lbimm() { return (x(5, 1) << 1) + x(6, 1); } uint64_t rvc_lhimm() { return (x(5, 1) << 1); } - uint64_t rvc_sreg1() { return x(7, 3); } - uint64_t rvc_sreg2() { return x(2, 3); } + uint64_t rvc_r1sc() { return x(7, 3); } + uint64_t rvc_r2sc() { return x(2, 3); } uint64_t rvc_rlist() { return x(4, 4); } uint64_t rvc_spimm() { return x(2, 2) << 4; } diff --git a/riscv/decode_macros.h b/riscv/decode_macros.h index 88a05a9..fee8ae7 100644 --- a/riscv/decode_macros.h +++ b/riscv/decode_macros.h @@ -55,8 +55,8 @@ #define RVC_SP READ_REG(X_SP) // Zc* macros -#define RVC_SREG1 (Sn(insn.rvc_sreg1())) -#define RVC_SREG2 (Sn(insn.rvc_sreg2())) +#define RVC_R1S (Sn(insn.rvc_r1sc())) +#define RVC_R2S (Sn(insn.rvc_r2sc())) #define SP READ_REG(X_SP) #define RA READ_REG(X_RA) diff --git a/riscv/insns/cm_mva01s.h b/riscv/insns/cm_mva01s.h index c8d4284..6212a8e 100644 --- a/riscv/insns/cm_mva01s.h +++ b/riscv/insns/cm_mva01s.h @@ -1,6 +1,6 @@ require_extension(EXT_ZCMP); if (p->extension_enabled('E')) { - require((insn.rvc_sreg1() < 2) && (insn.rvc_sreg2() < 2)); + require((insn.rvc_r1sc() < 2) && (insn.rvc_r2sc() < 2)); } -WRITE_REG(X_A0, READ_REG(RVC_SREG1)); -WRITE_REG(X_A1, READ_REG(RVC_SREG2)); +WRITE_REG(X_A0, READ_REG(RVC_R1S)); +WRITE_REG(X_A1, READ_REG(RVC_R2S)); diff --git a/riscv/insns/cm_mvsa01.h b/riscv/insns/cm_mvsa01.h index 1822bc1..949d2f8 100644 --- a/riscv/insns/cm_mvsa01.h +++ b/riscv/insns/cm_mvsa01.h @@ -1,6 +1,6 @@ require_extension(EXT_ZCMP); if (p->extension_enabled('E')) { - require((insn.rvc_sreg1() < 2) && (insn.rvc_sreg2() < 2)); + require((insn.rvc_r1sc() < 2) && (insn.rvc_r2sc() < 2)); } -WRITE_REG(RVC_SREG1, READ_REG(X_A0)); -WRITE_REG(RVC_SREG2, READ_REG(X_A1)); +WRITE_REG(RVC_R1S, READ_REG(X_A0)); +WRITE_REG(RVC_R2S, READ_REG(X_A1)); |