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| author | Eric Gouriou <ego@rivosinc.com> | 2023-06-01 18:07:38 -0700 |
|---|---|---|
| committer | Eric Gouriou <ego@rivosinc.com> | 2023-06-19 14:30:35 -0700 |
| commit | eadb0e1129c23e709b0565740f0fc1a3359de7b7 (patch) | |
| tree | 31e8a5fe6fa88892be4a330f8be2739d4d243119 /riscv/zvksed_ext_macros.h | |
| parent | 00873aa61acae4a17c1d269cddf1885e83b50102 (diff) | |
| download | riscv-isa-sim-eadb0e1129c23e709b0565740f0fc1a3359de7b7.zip riscv-isa-sim-eadb0e1129c23e709b0565740f0fc1a3359de7b7.tar.gz riscv-isa-sim-eadb0e1129c23e709b0565740f0fc1a3359de7b7.tar.bz2 | |
Zvk: Implement Zvkned, vector AES single round
Implement the Zvkned extension, "NIST Suite: Vector AES Encryption
& Decryption (Single Round)".
- vaeskf1.vi: AES forward key scheduling, AES-128.
- vaeskf2.vi: AES forward key scheduling, AES-256.
- vaesz.vs: AES encryption/decryption, 0-th round.
- vaesdm.{vs,vv}: AES decryption, middle rounds.
- vaesdf.{vs,vv}: AES decryption, final round.
- vaesem.{vs,vv}: AES encryption, middle rounds.
- vaesef.{vs,vv}: AES encryption, final round.
An extension specific header containing common logic is added.
Co-authored-by: Stanislaw Kardach <kda@semihalf.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
Diffstat (limited to 'riscv/zvksed_ext_macros.h')
0 files changed, 0 insertions, 0 deletions