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| author | Andrew Waterman <andrew@sifive.com> | 2026-02-25 22:45:34 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-02-25 22:45:34 -0800 |
| commit | 591cff16109ced6a21bb2a612a3853b4e9cbd86d (patch) | |
| tree | 78ec9949e3beb269dc587cbab69ba0f859897181 /riscv/vector_unit.cc | |
| parent | ae1531c207eccfe11d6009d39ab7998a93dfb139 (diff) | |
| parent | a437348306077d0ee26353faba73a8b639ece2a2 (diff) | |
| download | riscv-isa-sim-master.zip riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 | |
Only set mstatus.VS for legal vector instructions
Diffstat (limited to 'riscv/vector_unit.cc')
| -rw-r--r-- | riscv/vector_unit.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/riscv/vector_unit.cc b/riscv/vector_unit.cc index a7ba018..6eadf59 100644 --- a/riscv/vector_unit.cc +++ b/riscv/vector_unit.cc @@ -89,7 +89,6 @@ reg_t vectorUnit_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t new vl->write_raw(std::min(reqVL, vlmax)); } - vstart->write_raw(0); return vl->read(); } |