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author | ksco <numbksco@gmail.com> | 2022-08-11 17:45:06 +0800 |
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committer | GitHub <noreply@github.com> | 2022-08-11 02:45:06 -0700 |
commit | f04675c96c5c4668848431f4c729363060ce13e7 (patch) | |
tree | ec81811324097f1f3db96c6ade60b5ba036e6690 /riscv/v_ext_macros.h | |
parent | 6dcef28ed23f26d8f57880a3763f7a85da9fd08b (diff) | |
download | riscv-isa-sim-f04675c96c5c4668848431f4c729363060ce13e7.zip riscv-isa-sim-f04675c96c5c4668848431f4c729363060ce13e7.tar.gz riscv-isa-sim-f04675c96c5c4668848431f4c729363060ce13e7.tar.bz2 |
Remove dead code in VI_VV_EXT macro (#1065)
Diffstat (limited to 'riscv/v_ext_macros.h')
-rw-r--r-- | riscv/v_ext_macros.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 19207f7..3f9b4af 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -1468,9 +1468,6 @@ reg_t index[P.VU.vlmax]; \ case 0x84: \ P.VU.elt<type##64_t>(rd_num, i, true) = P.VU.elt<type##32_t>(rs2_num, i); \ break; \ - case 0x88: \ - P.VU.elt<type##64_t>(rd_num, i, true) = P.VU.elt<type##32_t>(rs2_num, i); \ - break; \ default: \ break; \ } \ |