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| author | Eric Gouriou <ego@rivosinc.com> | 2023-06-18 17:10:53 -0700 |
|---|---|---|
| committer | Eric Gouriou <ego@rivosinc.com> | 2023-06-19 14:30:03 -0700 |
| commit | d5c0339484323b5a9498576d70ec90eab2e13438 (patch) | |
| tree | ad788f77140ff7eaf07ec75c5369441e9589dc29 /riscv/v_ext_macros.h | |
| parent | 1e5a71f99b3432ba9fb543995a466c2d96e96cec (diff) | |
| download | riscv-isa-sim-d5c0339484323b5a9498576d70ec90eab2e13438.zip riscv-isa-sim-d5c0339484323b5a9498576d70ec90eab2e13438.tar.gz riscv-isa-sim-d5c0339484323b5a9498576d70ec90eab2e13438.tar.bz2 | |
Zvk: Infrastructure for Zvk extensions, element group handling
Introduce types and macros useful across multiple Zvk sub-extensions,
including Zvbb and Zvbc. Those will be used by upcoming
per-sub-extension commits.
In particular we introduce "Element Group" types and loop macros handling
those element groups. The concept of element group is described in
<https://github.com/riscv/riscv-crypto/blob/master/doc/vector/riscv-crypto-vector-element-groups.adoc>.
Note that the element group access method is not implemented
for WORDS_BIGENDIAN setup. As such, isa_parser.cc is modified to emit
an error when WORDS_BIGENDIAN is defined and extensions using element
groups are enabled.
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
Diffstat (limited to 'riscv/v_ext_macros.h')
| -rw-r--r-- | riscv/v_ext_macros.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 41256c7..908ff16 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -325,6 +325,10 @@ static inline bool is_overlapped_widen(const int astart, int asize, type_usew_t<x>::type vs1 = P.VU.elt<type_usew_t<x>::type>(rs1_num, i); \ type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); +#define V_U_PARAMS(x) \ + type_usew_t<x>::type &vd = P.VU.elt<type_usew_t<x>::type>(rd_num, i, true); \ + type_usew_t<x>::type vs2 = P.VU.elt<type_usew_t<x>::type>(rs2_num, i); + #define VX_U_PARAMS(x) \ type_usew_t<x>::type &vd = P.VU.elt<type_usew_t<x>::type>(rd_num, i, true); \ type_usew_t<x>::type rs1 = (type_usew_t<x>::type)RS1; \ @@ -693,6 +697,24 @@ static inline bool is_overlapped_widen(const int astart, int asize, } \ VI_LOOP_END +#define VI_V_ULOOP(BODY) \ + VI_CHECK_SSS(false) \ + VI_LOOP_BASE \ + if (sew == e8) { \ + V_U_PARAMS(e8); \ + BODY; \ + } else if (sew == e16) { \ + V_U_PARAMS(e16); \ + BODY; \ + } else if (sew == e32) { \ + V_U_PARAMS(e32); \ + BODY; \ + } else if (sew == e64) { \ + V_U_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + #define VI_VX_ULOOP(BODY) \ VI_CHECK_SSS(false) \ VI_LOOP_BASE \ |