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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-19 18:05:13 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:34:18 -0700 |
| commit | 8d40946475d73ce2627549b1857991d70cb1186b (patch) | |
| tree | 1ced84ca56e4ee7dfa11efbd593af4b805bd6d72 /riscv/v_ext_macros.h | |
| parent | 7b52a249c8259e1968e6edeec3fbd673c0e55dd5 (diff) | |
| download | riscv-isa-sim-8d40946475d73ce2627549b1857991d70cb1186b.zip riscv-isa-sim-8d40946475d73ce2627549b1857991d70cb1186b.tar.gz riscv-isa-sim-8d40946475d73ce2627549b1857991d70cb1186b.tar.bz2 | |
Template-ize AMOs
Diffstat (limited to 'riscv/v_ext_macros.h')
| -rw-r--r-- | riscv/v_ext_macros.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index ad31938..45c6cad 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -1409,14 +1409,14 @@ reg_t index[P.VU.vlmax]; \ switch (P.VU.vsew) { \ case e32: { \ auto vs3 = P.VU.elt< type ## 32_t>(vd, vreg_inx); \ - auto val = MMU.amo_uint32(baseAddr + index[i], [&](type ## 32_t UNUSED lhs) { op }); \ + auto val = MMU.amo<uint32_t>(baseAddr + index[i], [&](type ## 32_t UNUSED lhs) { op }); \ if (insn.v_wd()) \ P.VU.elt< type ## 32_t>(vd, vreg_inx, true) = val; \ } \ break; \ case e64: { \ auto vs3 = P.VU.elt< type ## 64_t>(vd, vreg_inx); \ - auto val = MMU.amo_uint64(baseAddr + index[i], [&](type ## 64_t UNUSED lhs) { op }); \ + auto val = MMU.amo<uint64_t>(baseAddr + index[i], [&](type ## 64_t UNUSED lhs) { op }); \ if (insn.v_wd()) \ P.VU.elt< type ## 64_t>(vd, vreg_inx, true) = val; \ } \ |