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| author | liweiwei <liweiwei@iscas.ac.cn> | 2021-10-14 09:49:10 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-04 10:11:26 +0800 |
| commit | 5de0c89c034cf64fdab8e36d2dc7488aa035d823 (patch) | |
| tree | b5ed8f034d95a2fb22e7ec64d13c73484c2c059b /riscv/v_ext_macros.h | |
| parent | 7812b01154c6a2f19e0d4bc9f00e5d5fcb9aec22 (diff) | |
| download | riscv-isa-sim-5de0c89c034cf64fdab8e36d2dc7488aa035d823.zip riscv-isa-sim-5de0c89c034cf64fdab8e36d2dc7488aa035d823.tar.gz riscv-isa-sim-5de0c89c034cf64fdab8e36d2dc7488aa035d823.tar.bz2 | |
Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min} instructions
change the extention check for F/D/Zfh instructions
modify the F/D/Zfh instructions to read X regs when enable Zfinx
Co-authored-by: wangmeng <shusheng8495@hotmail.com>
Diffstat (limited to 'riscv/v_ext_macros.h')
| -rw-r--r-- | riscv/v_ext_macros.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 1a2a734..9ff383c 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -1802,7 +1802,7 @@ reg_t index[P.VU.vlmax]; \ case e16: { \ float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \ float32_t vs2 = f16_to_f32(P.VU.elt<float16_t>(rs2_num, i)); \ - float32_t rs1 = f16_to_f32(f16(READ_FREG(rs1_num))); \ + float32_t rs1 = f16_to_f32(FRS1_H); \ BODY16; \ set_fp_exceptions; \ break; \ @@ -1810,7 +1810,7 @@ reg_t index[P.VU.vlmax]; \ case e32: { \ float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \ float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \ - float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \ + float64_t rs1 = f32_to_f64(FRS1_F); \ BODY32; \ set_fp_exceptions; \ break; \ @@ -1856,7 +1856,7 @@ reg_t index[P.VU.vlmax]; \ case e16: { \ float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \ float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \ - float32_t rs1 = f16_to_f32(f16(READ_FREG(rs1_num))); \ + float32_t rs1 = f16_to_f32(FRS1_H); \ BODY16; \ set_fp_exceptions; \ break; \ @@ -1864,7 +1864,7 @@ reg_t index[P.VU.vlmax]; \ case e32: { \ float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \ float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \ - float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \ + float64_t rs1 = f32_to_f64(FRS1_F); \ BODY32; \ set_fp_exceptions; \ break; \ |