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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-01 16:09:02 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-07 08:31:11 +0800 |
| commit | 2aedbdd01911a42565cd6d154f82fa00a66410cd (patch) | |
| tree | 441ee02f16e3e3faa9fcf88b826899c391b4e13b /riscv/v_ext_macros.h | |
| parent | ac466a21df442c59962589ba296c702631e041b5 (diff) | |
| download | riscv-isa-sim-2aedbdd01911a42565cd6d154f82fa00a66410cd.zip riscv-isa-sim-2aedbdd01911a42565cd6d154f82fa00a66410cd.tar.gz riscv-isa-sim-2aedbdd01911a42565cd6d154f82fa00a66410cd.tar.bz2 | |
remove multi blank lines
Diffstat (limited to 'riscv/v_ext_macros.h')
| -rw-r--r-- | riscv/v_ext_macros.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 4df6813..1a2a734 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -201,7 +201,6 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) if (is_over) \ require(insn.rd() != insn.rs2()); \ - // // vector: loop header and end helper // @@ -291,7 +290,6 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) require(!(insn.rd() == 0 && P.VU.vflmul > 1)); \ }); - #define INT_ROUNDING(result, xrm, gb) \ do { \ const uint64_t lsb = 1UL << (gb); \ @@ -656,7 +654,6 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) REDUCTION_ULOOP(e64, BODY) \ } - // genearl VXI signed/unsigned loop #define VI_VV_ULOOP(BODY) \ VI_CHECK_SSS(true) \ @@ -1825,7 +1822,6 @@ reg_t index[P.VU.vlmax]; \ DEBUG_RVV_FP_VV; \ VI_VFP_LOOP_END - #define VI_VFP_VV_LOOP_WIDE(BODY16, BODY32) \ VI_CHECK_DSS(true); \ VI_VFP_LOOP_BASE \ |