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author | YenHaoChen <howard25336284@gmail.com> | 2023-01-11 18:44:02 +0800 |
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committer | YenHaoChen <howard25336284@gmail.com> | 2023-01-30 21:15:15 +0800 |
commit | f8856e4d4f5a62bcc04234a2007910c20b0ca185 (patch) | |
tree | 0efd19de21f365b3dccb43f889530e6f7acb9711 /riscv/triggers.h | |
parent | 4fb1389b17ee42452bb5d9dbf0118ec8f73518d2 (diff) | |
download | riscv-isa-sim-f8856e4d4f5a62bcc04234a2007910c20b0ca185.zip riscv-isa-sim-f8856e4d4f5a62bcc04234a2007910c20b0ca185.tar.gz riscv-isa-sim-f8856e4d4f5a62bcc04234a2007910c20b0ca185.tar.bz2 |
triggers: add icount_t and update tinfo
Diffstat (limited to 'riscv/triggers.h')
-rw-r--r-- | riscv/triggers.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/riscv/triggers.h b/riscv/triggers.h index bc64c4d..85842e3 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -233,6 +233,22 @@ public: virtual void tdata1_write(processor_t * const proc, const reg_t val, const bool allow_chain) noexcept override; }; +class icount_t : public trigger_t { +public: + virtual reg_t tdata1_read(const processor_t * const proc) const noexcept override; + virtual void tdata1_write(processor_t * const proc, const reg_t val, const bool allow_chain) noexcept override; + + bool get_dmode() const override { return dmode; } + virtual action_t get_action() const override { return action; } + +private: + bool dmode; + bool hit; + unsigned count; + bool pending; + action_t action; +}; + class module_t { public: module_t(unsigned count); |