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| author | Atul Khare <atulkhare@rivosinc.com> | 2023-05-17 12:40:01 -0700 |
|---|---|---|
| committer | Atul Khare <atulkhare@rivosinc.com> | 2023-05-24 09:15:27 -0700 |
| commit | 31f5ede662303183d93f80e869379e49b7a01608 (patch) | |
| tree | b1f76dd7e83430ac0626ff66fdcc8ae605d6c177 /riscv/triggers.h | |
| parent | ddae0f25a89f2d04d76a222505d00c39dc511505 (diff) | |
| download | riscv-isa-sim-31f5ede662303183d93f80e869379e49b7a01608.zip riscv-isa-sim-31f5ede662303183d93f80e869379e49b7a01608.tar.gz riscv-isa-sim-31f5ede662303183d93f80e869379e49b7a01608.tar.bz2 | |
Enhance mode_match() functionality
The current version of mode_match() is based on the current privilege
level. This adds an explicit privilege and virtual mode parameters in
anticipation of an upcoming patch for matching trap triggers.
Diffstat (limited to 'riscv/triggers.h')
| -rw-r--r-- | riscv/triggers.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/triggers.h b/riscv/triggers.h index aeda4d5..94e7e5c 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -102,7 +102,7 @@ protected: private: unsigned legalize_mhselect(bool h_enabled) const noexcept; - bool mode_match(state_t * const state) const noexcept; + bool mode_match(reg_t prv, bool v) const noexcept; bool textra_match(processor_t * const proc) const noexcept; struct mhselect_interpretation { |