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author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-04-09 19:45:10 -0700 |
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committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-04-09 20:18:35 -0700 |
commit | 68f504c52e8d6e2a89422fdce6c2e8343ec6ddef (patch) | |
tree | b023c49ed9c6a75dcc684720d3757c45bb5199bf /riscv/trap.h | |
parent | e9567ce7bbcdd59cc6e6bc2133a1680c1598cb04 (diff) | |
download | riscv-isa-sim-68f504c52e8d6e2a89422fdce6c2e8343ec6ddef.zip riscv-isa-sim-68f504c52e8d6e2a89422fdce6c2e8343ec6ddef.tar.gz riscv-isa-sim-68f504c52e8d6e2a89422fdce6c2e8343ec6ddef.tar.bz2 |
[sim] add vector traps to vector instructions
Diffstat (limited to 'riscv/trap.h')
-rw-r--r-- | riscv/trap.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/trap.h b/riscv/trap.h index a5c3212..8424d80 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -13,7 +13,7 @@ DECLARE_TRAP(data_address_misaligned), \ DECLARE_TRAP(load_access_fault), \ DECLARE_TRAP(store_access_fault), \ - DECLARE_TRAP(trap_vector_disabled), \ + DECLARE_TRAP(vector_disabled), \ DECLARE_TRAP(reserved2), \ DECLARE_TRAP(reserved3), \ DECLARE_TRAP(reserved4), \ |