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author | Andrew Waterman <andrew@sifive.com> | 2017-11-27 14:18:06 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2017-11-27 14:18:06 -0800 |
commit | 160c1a5cee45d3842824af565e52458e2f8b3c48 (patch) | |
tree | 43e7764709dddaee8c6eaaf482fb196e8b92ba76 /riscv/trap.h | |
parent | d7ceeabbe6bb2bfc153c6b8d9a1db98f0c975347 (diff) | |
download | riscv-isa-sim-160c1a5cee45d3842824af565e52458e2f8b3c48.zip riscv-isa-sim-160c1a5cee45d3842824af565e52458e2f8b3c48.tar.gz riscv-isa-sim-160c1a5cee45d3842824af565e52458e2f8b3c48.tar.bz2 |
Set tval to 0 on traps with no specified tval
Simply not writing the register was not a conformant implementation.
Diffstat (limited to 'riscv/trap.h')
-rw-r--r-- | riscv/trap.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/trap.h b/riscv/trap.h index 91e5223..1fe44eb 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -14,7 +14,7 @@ class trap_t trap_t(reg_t which) : which(which) {} virtual const char* name(); virtual bool has_badaddr() { return false; } - virtual reg_t get_badaddr() { abort(); } + virtual reg_t get_badaddr() { return 0; } reg_t cause() { return which; } private: char _name[16]; |