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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-17 01:19:40 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-17 01:19:40 -0700 |
| commit | 1fbcb3dfe3a8776cbe742cf7c8299186d6b4bec9 (patch) | |
| tree | a8b4af2990c5fd0762a63517254dfb1f6079fbc2 /riscv/trap.h | |
| parent | c0f7d3cd7760f6021a87027a2bb95039daa92c4a (diff) | |
| download | riscv-isa-sim-1fbcb3dfe3a8776cbe742cf7c8299186d6b4bec9.zip riscv-isa-sim-1fbcb3dfe3a8776cbe742cf7c8299186d6b4bec9.tar.gz riscv-isa-sim-1fbcb3dfe3a8776cbe742cf7c8299186d6b4bec9.tar.bz2 | |
Merge [shm]call into ecall, [shm]ret into eret
Diffstat (limited to 'riscv/trap.h')
| -rw-r--r-- | riscv/trap.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/riscv/trap.h b/riscv/trap.h index 8bc94f3..aa4a4e1 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -45,13 +45,11 @@ class mem_trap_t : public trap_t DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault) DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) -DECLARE_TRAP(CAUSE_SCALL, scall) -DECLARE_TRAP(CAUSE_HCALL, hcall) -DECLARE_TRAP(CAUSE_MCALL, mcall) -DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FAULT_LOAD, load_access_fault) DECLARE_MEM_TRAP(CAUSE_FAULT_STORE, store_access_fault) +DECLARE_TRAP(CAUSE_ECALL, ecall) +DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint) #endif |