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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2022-12-13 16:26:11 -0800 |
|---|---|---|
| committer | Jerry Zhao <jerryz123@berkeley.edu> | 2022-12-15 14:02:39 -0800 |
| commit | ebc936767735fcd152cf51e6223dc2294b658d92 (patch) | |
| tree | 4a924e0165da54d1f1220caf0d277a0b443a2810 /riscv/riscv.mk.in | |
| parent | d00c01d2af6c141c0a9147533323582e6491e9c3 (diff) | |
| download | riscv-isa-sim-ebc936767735fcd152cf51e6223dc2294b658d92.zip riscv-isa-sim-ebc936767735fcd152cf51e6223dc2294b658d92.tar.gz riscv-isa-sim-ebc936767735fcd152cf51e6223dc2294b658d92.tar.bz2 | |
Add cfg.cc to hold internal implementation of mem_cfg_t
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index efe2bd0..5b7c824 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -98,6 +98,7 @@ riscv_srcs = \ triggers.cc \ vector_unit.cc \ socketif.cc \ + cfg.cc \ $(riscv_gen_srcs) \ riscv_test_srcs = |