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| author | Rupert Swarbrick <rswarbrick@gmail.com> | 2022-03-29 20:21:21 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-03-29 12:21:21 -0700 |
| commit | cd2bc70a5d010161588f3cebcd2891514337e059 (patch) | |
| tree | b2f666466fca5527f687bd7b86061d3ba7429cb8 /riscv/riscv.mk.in | |
| parent | 9a43019bfff59da7c42f1a95c636dd5ff5ec7f32 (diff) | |
| download | riscv-isa-sim-cd2bc70a5d010161588f3cebcd2891514337e059.zip riscv-isa-sim-cd2bc70a5d010161588f3cebcd2891514337e059.tar.gz riscv-isa-sim-cd2bc70a5d010161588f3cebcd2891514337e059.tar.bz2 | |
Split isa_parser_t out of processor.* and into its own file (#955)
The main motivation for this is that we want to move the ISA parsing
logic to run before we even construct a simulator. That's probably a
bit nicer if we don't depend on the processor header.
It also means that we can stop depending on processor.h in disasm.cc
or spike_log_parser.cc (both through disasm.h), which feels a bit
cleaner: making sense of an instruction trace shouldn't really require
knowledge of the internal state of a processor.
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index a803b2a..ecbda5d 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -39,6 +39,7 @@ riscv_precompiled_hdrs = \ insn_template.h \ riscv_srcs = \ + isa_parser.cc \ processor.cc \ execute.cc \ dts.cc \ |