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| author | Eric Gouriou <ego@rivosinc.com> | 2023-06-01 18:07:53 -0700 |
|---|---|---|
| committer | Eric Gouriou <ego@rivosinc.com> | 2023-06-19 14:30:35 -0700 |
| commit | cbb2b1a224d8922c6d3146da56f5087a3858ced5 (patch) | |
| tree | 290184b604a1538fd1904155c02f9161e1ee4856 /riscv/riscv.mk.in | |
| parent | eadb0e1129c23e709b0565740f0fc1a3359de7b7 (diff) | |
| download | riscv-isa-sim-cbb2b1a224d8922c6d3146da56f5087a3858ced5.zip riscv-isa-sim-cbb2b1a224d8922c6d3146da56f5087a3858ced5.tar.gz riscv-isa-sim-cbb2b1a224d8922c6d3146da56f5087a3858ced5.tar.bz2 | |
Zvk: Implement Zvksed, vector SM4 Block Cipher
Implement the Zvksed sub-extension, "ShangMi Suite: SM4 Block Cipher":
- vsm4k.vi, vector SM4 key expansion,
- vsm4r.{vs,vv}, vector SM4 rounds.
This also introduces a header for common vector SM4 logic.
Co-authored-by: Raghav Gupta <rgupta@rivosinc.com>
Co-authored-by: Albert Jakieła <aja@semihalf.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 2d75662..c774e1b 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -1387,12 +1387,18 @@ riscv_insn_ext_zvknh = \ vsha2ch_vv \ vsha2ms_vv \ +riscv_insn_ext_zvksed = \ + vsm4k_vi \ + vsm4r_vs \ + vsm4r_vv \ + riscv_insn_ext_zvk = \ $(riscv_insn_ext_zvbb) \ $(riscv_insn_ext_zvbc) \ $(riscv_insn_ext_zvkg) \ $(riscv_insn_ext_zvkned) \ $(riscv_insn_ext_zvknh) \ + $(riscv_insn_ext_zvksed) \ riscv_insn_list = \ $(if $(HAVE_INT128),$(riscv_insn_ext_v),) \ |