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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-14 22:47:51 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-05-29 09:01:21 +0800 |
| commit | 8aacc4effde92122a25beadac594162187767d7e (patch) | |
| tree | 30b7e944692422a945b83d3db3a1c81433686a54 /riscv/riscv.mk.in | |
| parent | 40dce7899b7a42d06413071c542606d4c0249174 (diff) | |
| download | riscv-isa-sim-8aacc4effde92122a25beadac594162187767d7e.zip riscv-isa-sim-8aacc4effde92122a25beadac594162187767d7e.tar.gz riscv-isa-sim-8aacc4effde92122a25beadac594162187767d7e.tar.bz2 | |
Add support for new instructions of Zvfbfmin extension
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 9e49c89..a83bec2 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -1363,8 +1363,13 @@ riscv_insn_ext_zfbfmin = \ fcvt_bf16_s \ fcvt_s_bf16 \ +riscv_insn_ext_zvfbfmin = \ + vfncvtbf16_f_f_w \ + vfwcvtbf16_f_f_v \ + riscv_insn_ext_bf16 = \ $(riscv_insn_ext_zfbfmin) \ + $(riscv_insn_ext_zvfbfmin) \ riscv_insn_list = \ $(riscv_insn_ext_a) \ |