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| author | Anup Patel <anup.patel@wdc.com> | 2020-06-19 17:56:05 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-07-09 23:04:18 +0530 |
| commit | 564ed97f618321b8499a3e8837c36f622ee8a893 (patch) | |
| tree | 81754eab18ac55c64f7c2b3017c451d99bb9d457 /riscv/riscv.mk.in | |
| parent | b75aff9e5d132a16d9326bc0b3bbc724ae3c753c (diff) | |
| download | riscv-isa-sim-564ed97f618321b8499a3e8837c36f622ee8a893.zip riscv-isa-sim-564ed97f618321b8499a3e8837c36f622ee8a893.tar.gz riscv-isa-sim-564ed97f618321b8499a3e8837c36f622ee8a893.tar.bz2 | |
Implement new instructions of hypervisor extension
We add new HFENCE, HLV, and HSV instructions for HS-mode which
are defined as part of the RISC-V hypervisor extension.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 1aa3352..73c4cef 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -739,6 +739,23 @@ riscv_insn_ext_v = \ $(riscv_insn_ext_v_ctrl) \ $(riscv_insn_ext_v_ldst) \ +riscv_insn_ext_h = \ + hfence_gvma \ + hfence_vvma \ + hlv_b \ + hlv_bu \ + hlv_h \ + hlv_hu \ + hlvx_hu \ + hlv_w \ + hlv_wu \ + hlvx_wu \ + hlv_d \ + hsv_b \ + hsv_h \ + hsv_w \ + hsv_d \ + riscv_insn_priv = \ csrrc \ csrrci \ @@ -765,6 +782,7 @@ riscv_insn_list = \ $(riscv_insn_ext_zfh) \ $(riscv_insn_ext_q) \ $(if $(HAVE_INT128),$(riscv_insn_ext_v),) \ + $(riscv_insn_ext_h) \ $(riscv_insn_priv) \ riscv_gen_srcs = \ |