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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-03-17 20:38:34 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-04-03 16:55:14 -0700 |
| commit | 09140c07e13ddd3951c231e1fb7cbe2d3d41f7aa (patch) | |
| tree | 36b92616ad46d34ab23606a883f6e835a11f0f2d /riscv/riscv.mk.in | |
| parent | f002b931d076af91c35dad05dd54580112b4a9d6 (diff) | |
| download | riscv-isa-sim-09140c07e13ddd3951c231e1fb7cbe2d3d41f7aa.zip riscv-isa-sim-09140c07e13ddd3951c231e1fb7cbe2d3d41f7aa.tar.gz riscv-isa-sim-09140c07e13ddd3951c231e1fb7cbe2d3d41f7aa.tar.bz2 | |
Implement Zfa.
This passes our developer test suite, when comparing output
(signature) against the SAIL implementation.
If any corner-cases require additional changes after ACT goes
upstream, we can apply an add-on patch.
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index f64711a..f1b29aa 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -239,6 +239,15 @@ riscv_insn_ext_f = \ fsub_s \ fsw \ +riscv_insn_ext_f_zfa= \ + fli_s \ + fmaxm_s \ + fminm_s \ + fround_s \ + froundnx_s \ + fleq_s \ + fltq_s + riscv_insn_ext_d = \ fadd_d \ fclass_d \ @@ -274,6 +283,18 @@ riscv_insn_ext_d = \ fsqrt_d \ fsub_d \ +riscv_insn_ext_d_zfa = \ + fli_d \ + fmaxm_d \ + fminm_d \ + fround_d \ + froundnx_d \ + fmvh_x_d \ + fmvp_d_x \ + fcvtmod_w_d \ + fleq_d \ + fltq_d + riscv_insn_ext_zfh = \ fadd_h \ fclass_h \ @@ -312,6 +333,15 @@ riscv_insn_ext_zfh = \ fsqrt_h \ fsub_h \ +riscv_insn_ext_zfh_zfa = \ + fli_h \ + fmaxm_h \ + fminm_h \ + fround_h \ + froundnx_h \ + fleq_h \ + fltq_h + riscv_insn_ext_q = \ fadd_q \ fclass_q \ @@ -345,6 +375,17 @@ riscv_insn_ext_q = \ fsqrt_q \ fsub_q \ +riscv_insn_ext_q_zfa = \ + fli_q \ + fmaxm_q \ + fminm_q \ + fround_q \ + froundnx_q \ + fmvh_x_q \ + fmvp_q_x \ + fleq_q \ + fltq_q + riscv_insn_ext_b = \ add_uw \ andn \ @@ -1321,9 +1362,13 @@ riscv_insn_list = \ $(riscv_insn_ext_i) \ $(riscv_insn_ext_m) \ $(riscv_insn_ext_f) \ + $(riscv_insn_ext_f_zfa) \ $(riscv_insn_ext_d) \ + $(riscv_insn_ext_d_zfa) \ $(riscv_insn_ext_zfh) \ + $(riscv_insn_ext_zfh_zfa) \ $(riscv_insn_ext_q) \ + $(riscv_insn_ext_q_zfa) \ $(riscv_insn_ext_b) \ $(riscv_insn_ext_k) \ $(if $(HAVE_INT128),$(riscv_insn_ext_v),) \ |