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| author | Andrew Waterman <andrew@sifive.com> | 2023-06-17 16:53:34 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-06-17 18:47:59 -0700 |
| commit | 057cfbcca6dc6c65f1fd69b754e499ccabebe273 (patch) | |
| tree | 2339c8e857268ff2fe83def41668a10c4a50fee2 /riscv/riscv.mk.in | |
| parent | e58d89aa2c38ca40e68ad4e010c91239c4794e00 (diff) | |
| download | riscv-isa-sim-057cfbcca6dc6c65f1fd69b754e499ccabebe273.zip riscv-isa-sim-057cfbcca6dc6c65f1fd69b754e499ccabebe273.tar.gz riscv-isa-sim-057cfbcca6dc6c65f1fd69b754e499ccabebe273.tar.bz2 | |
Add test that ensures opcodes don't overlap unless explicitly specified
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 1cfe627..ac45b28 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -75,7 +75,8 @@ riscv_srcs = \ cfg.cc \ $(riscv_gen_srcs) \ -riscv_test_srcs = +riscv_test_srcs = \ + check-opcode-overlap.t.cc \ riscv_gen_hdrs = \ insn_list.h \ |