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| author | Marcus Comstedt <marcus@mc.pp.se> | 2020-10-11 13:36:13 +0200 |
|---|---|---|
| committer | Marcus Comstedt <marcus@mc.pp.se> | 2020-11-07 15:03:58 +0100 |
| commit | 8d09d845a7373cce52d3943f5dca1a2ac34a4f83 (patch) | |
| tree | 65a8e157ac2c167c6b89d436c00fa8c12bdf6181 /riscv/riscv.ac | |
| parent | 641d7d03e6a8d822b720fcb1a19f261813c00c4a (diff) | |
| download | riscv-isa-sim-8d09d845a7373cce52d3943f5dca1a2ac34a4f83.zip riscv-isa-sim-8d09d845a7373cce52d3943f5dca1a2ac34a4f83.tar.gz riscv-isa-sim-8d09d845a7373cce52d3943f5dca1a2ac34a4f83.tar.bz2 | |
Implement support for big-endian targets
Diffstat (limited to 'riscv/riscv.ac')
| -rw-r--r-- | riscv/riscv.ac | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/riscv.ac b/riscv/riscv.ac index 64693e9..a43bcd6 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -45,3 +45,8 @@ AC_ARG_ENABLE([misaligned], AS_HELP_STRING([--enable-misaligned], [Enable hardwa AS_IF([test "x$enable_misaligned" = "xyes"], [ AC_DEFINE([RISCV_ENABLE_MISALIGNED],,[Enable hardware support for misaligned loads and stores]) ]) + +AC_ARG_ENABLE([dual-endian], AS_HELP_STRING([--enable-dual-endian], [Enable support for running target in either endianness])) +AS_IF([test "x$enable_dual_endian" = "xyes"], [ + AC_DEFINE([RISCV_ENABLE_DUAL_ENDIAN],,[Enable support for running target in either endianness]) +]) |