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| author | Andrew Waterman <andrew@sifive.com> | 2022-02-16 05:02:41 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-02-16 05:02:41 -0800 |
| commit | 8cc6ebead30e00912fa1d254840b6288a16a2a23 (patch) | |
| tree | dc853266bc4ae5655b349171504734cb82946491 /riscv/processor.h | |
| parent | e03fa93c988ec92b6f1427b5cc10c40b41351e70 (diff) | |
| parent | b68b758b251645c89408c7cd1ce4bd2a2d55889c (diff) | |
| download | riscv-isa-sim-8cc6ebead30e00912fa1d254840b6288a16a2a23.zip riscv-isa-sim-8cc6ebead30e00912fa1d254840b6288a16a2a23.tar.gz riscv-isa-sim-8cc6ebead30e00912fa1d254840b6288a16a2a23.tar.bz2 | |
Merge branch 'plctlab-plct-cmo-upstream'
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index aa98644..d4a42b2 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -218,6 +218,11 @@ struct state_t csr_t_p fflags; csr_t_p frm; + + csr_t_p menvcfg; + csr_t_p senvcfg; + csr_t_p henvcfg; + bool serialized; // whether timer CSRs are in a well-defined state // When true, execute a single instruction and then enter debug mode. This @@ -273,6 +278,8 @@ typedef enum { EXT_ZHINX, EXT_ZHINXMIN, EXT_XBITMANIP, + EXT_ZICBOM, + EXT_ZICBOZ, } isa_extension_t; typedef enum { |