aboutsummaryrefslogtreecommitdiff
path: root/riscv/processor.h
diff options
context:
space:
mode:
authorAndrew Waterman <andrew@sifive.com>2024-05-31 01:24:02 -0700
committerAndrew Waterman <andrew@sifive.com>2024-05-31 01:24:02 -0700
commit759599553bab6c95399253ba366a0f5b1b3dd48f (patch)
tree8f84650d9d8c783ee582c8d2956cce995fd8dca1 /riscv/processor.h
parent148e6d63e036a611537f7afbee771d9b83d348fb (diff)
downloadriscv-isa-sim-759599553bab6c95399253ba366a0f5b1b3dd48f.zip
riscv-isa-sim-759599553bab6c95399253ba366a0f5b1b3dd48f.tar.gz
riscv-isa-sim-759599553bab6c95399253ba366a0f5b1b3dd48f.tar.bz2
Avoid checking ELP before every instruction fetch
Serialize after setting ELP. That way, we can hoist the check outside of the main simulation loop.
Diffstat (limited to 'riscv/processor.h')
-rw-r--r--riscv/processor.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h
index f3e5294..3e37b43 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -319,7 +319,7 @@ public:
void clear_waiting_for_interrupt() { in_wfi = false; };
bool is_waiting_for_interrupt() { return in_wfi; };
- void execute_insn_prehook(insn_t insn);
+ void check_if_lpad_required();
private:
const isa_parser_t * const isa;