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| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | 2022-04-11 19:52:27 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-04-11 11:52:27 -0700 |
| commit | 168b4ea6a568741e88156ed8f96b5df2765d9df7 (patch) | |
| tree | 89cfee274199fd22294860f07972118dabf99f02 /riscv/processor.h | |
| parent | 7dc9283f31680a32110ad7f7296bde195c86399e (diff) | |
| download | riscv-isa-sim-168b4ea6a568741e88156ed8f96b5df2765d9df7.zip riscv-isa-sim-168b4ea6a568741e88156ed8f96b5df2765d9df7.tar.gz riscv-isa-sim-168b4ea6a568741e88156ed8f96b5df2765d9df7.tar.bz2 | |
Split mem layout computation in spike.cc (#957)
The motivation here is mostly to enable a refactoring where the memory
layout (sans allocated memory) gets passed to DTS/DTB code before we
ever allocate anything.
But it turns out to make merge_overlapping_memory_regions a bit
simpler, which is an added bonus.
Diffstat (limited to 'riscv/processor.h')
0 files changed, 0 insertions, 0 deletions