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| author | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-22 17:54:30 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-26 17:17:52 -0700 |
| commit | c3f918afad4e57ba9dcc2eb4c00ebb76e981108a (patch) | |
| tree | 96f68280d9fdf664096fa84c04eb6b83316f122f /riscv/processor.h | |
| parent | 2c9648735e5f7ba6d3e68bd20f6b9b599743016c (diff) | |
| download | riscv-isa-sim-c3f918afad4e57ba9dcc2eb4c00ebb76e981108a.zip riscv-isa-sim-c3f918afad4e57ba9dcc2eb4c00ebb76e981108a.tar.gz riscv-isa-sim-c3f918afad4e57ba9dcc2eb4c00ebb76e981108a.tar.bz2 | |
Convert dpc to csr_t
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index bd1c85b..36422b3 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -201,7 +201,7 @@ struct state_t csr_t_p vstval; csr_t_p vsatp; - reg_t dpc; + csr_t_p dpc; dcsr_t dcsr; csr_t_p tselect; mcontrol_t mcontrol[num_triggers]; |