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| author | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-29 13:08:37 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-09-29 14:32:29 -0700 |
| commit | 464a7fb56a9152bc16a7ae5e519a3d21781f02a1 (patch) | |
| tree | fba0c0fd34fa45a5301a9019ce96f8d49a134c46 /riscv/processor.h | |
| parent | 72a6f9fac8f3c058d72af54a8554ee6fab2627ec (diff) | |
| download | riscv-isa-sim-464a7fb56a9152bc16a7ae5e519a3d21781f02a1.zip riscv-isa-sim-464a7fb56a9152bc16a7ae5e519a3d21781f02a1.tar.gz riscv-isa-sim-464a7fb56a9152bc16a7ae5e519a3d21781f02a1.tar.bz2 | |
Convert vxrm to csr_t
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index f2b942f..0cc75b3 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -511,8 +511,8 @@ public: char reg_referenced[NVPR]; int setvl_count; reg_t vlmax; - reg_t vxrm, vl, vtype, vlenb; - vector_csr_t_p vstart, vxsat; + reg_t vl, vtype, vlenb; + vector_csr_t_p vxrm, vstart, vxsat; reg_t vma, vta; reg_t vsew; float vflmul; @@ -553,10 +553,10 @@ public: reg_referenced{0}, setvl_count(0), vlmax(0), - vxrm(0), vl(0), vtype(0), vlenb(0), + vxrm(0), vstart(0), vxsat(0), vma(0), @@ -581,7 +581,7 @@ public: reg_t get_slen() { return VLEN; } VRM get_vround_mode() { - return (VRM)vxrm; + return (VRM)(vxrm->read()); } }; |