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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-01-27 17:20:54 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-01-27 17:20:54 +0800 |
| commit | 3a16df6e04205a7053f639a93a6032df3805715b (patch) | |
| tree | 51938a368eb78e319b4d74b31771518d104ceac5 /riscv/processor.h | |
| parent | a68d310bcb066c031ce9121fabefc9ca6c8c8f80 (diff) | |
| download | riscv-isa-sim-3a16df6e04205a7053f639a93a6032df3805715b.zip riscv-isa-sim-3a16df6e04205a7053f639a93a6032df3805715b.tar.gz riscv-isa-sim-3a16df6e04205a7053f639a93a6032df3805715b.tar.bz2 | |
add disas support for zfinx, zdinx and zhinx{min}
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 5d5f51b..aa98644 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -268,6 +268,10 @@ typedef enum { EXT_SVNAPOT, EXT_SVPBMT, EXT_SVINVAL, + EXT_ZDINX, + EXT_ZFINX, + EXT_ZHINX, + EXT_ZHINXMIN, EXT_XBITMANIP, } isa_extension_t; |