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| author | Andrew Waterman <andrew@sifive.com> | 2023-05-18 21:48:53 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-05-18 21:48:53 -0700 |
| commit | 0e83fe66fbf7b918602476bbaacfa6198a90d337 (patch) | |
| tree | 93a72f8e0f093f1c872a0cacb2d822c166954bc0 /riscv/processor.h | |
| parent | 7a2ff14bff461f2c7adfbf407e11527f55d920db (diff) | |
| download | riscv-isa-sim-rivosinc-etrigger_fix_exception_match.zip riscv-isa-sim-rivosinc-etrigger_fix_exception_match.tar.gz riscv-isa-sim-rivosinc-etrigger_fix_exception_match.tar.bz2 | |
Call stash_privilege more selectivelyrivosinc-etrigger_fix_exception_match
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 914bd45..e37ff8b 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -298,6 +298,8 @@ public: void clear_waiting_for_interrupt() { in_wfi = false; }; bool is_waiting_for_interrupt() { return in_wfi; }; + void stash_privilege(); + private: const isa_parser_t * const isa; const cfg_t * const cfg; |