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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-21 00:34:20 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-12-21 01:14:02 -0800 |
| commit | b5f68dc55c2b310d24db35a3c7df1ad86509ab61 (patch) | |
| tree | 05d37c008d7d15b4f0d4a1d1f09408ca3c0425b5 /riscv/processor.cc | |
| parent | 7831b3e5f22602f373d580dd36b87a8aa02d2436 (diff) | |
| download | riscv-isa-sim-b5f68dc55c2b310d24db35a3c7df1ad86509ab61.zip riscv-isa-sim-b5f68dc55c2b310d24db35a3c7df1ad86509ab61.tar.gz riscv-isa-sim-b5f68dc55c2b310d24db35a3c7df1ad86509ab61.tar.bz2 | |
Remove --enable-histogram option
It's now redundant.
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 6e06408..2925478 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -519,13 +519,6 @@ void processor_t::set_debug(bool value) void processor_t::set_histogram(bool value) { histogram_enabled = value; -#ifndef RISCV_ENABLE_HISTOGRAM - if (value) { - fprintf(stderr, "PC Histogram support has not been properly enabled;"); - fprintf(stderr, " please re-build the riscv-isa-sim project using \"configure --enable-histogram\".\n"); - abort(); - } -#endif } void processor_t::enable_log_commits() |