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| author | YenHaoChen <howard25336284@gmail.com> | 2022-11-16 12:53:57 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2022-12-01 09:39:49 +0800 |
| commit | 7c208a6292ac097a03824af849f348ea000cc2d2 (patch) | |
| tree | 8b0c2c065bde4103202ad2cedd290a330b6c0135 /riscv/processor.cc | |
| parent | bbaad7a422198d616e72331d7274dbb9aa9cde9f (diff) | |
| download | riscv-isa-sim-7c208a6292ac097a03824af849f348ea000cc2d2.zip riscv-isa-sim-7c208a6292ac097a03824af849f348ea000cc2d2.tar.gz riscv-isa-sim-7c208a6292ac097a03824af849f348ea000cc2d2.tar.bz2 | |
triggers: add debug log of trigger action
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index cb2c1aa..8801062 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -923,6 +923,13 @@ void processor_t::take_trap(trap_t& t, reg_t epc) void processor_t::take_trigger_action(triggers::action_t action, reg_t breakpoint_tval, reg_t epc) { + if (debug) { + std::stringstream s; // first put everything in a string, later send it to output + s << "core " << std::dec << std::setfill(' ') << std::setw(3) << id + << ": trigger action " << (int)action << std::endl; + debug_output_log(&s); + } + switch (action) { case triggers::ACTION_DEBUG_MODE: enter_debug_mode(DCSR_CAUSE_HWBP); |