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| author | Andrew Waterman <andrew@sifive.com> | 2023-02-05 15:35:11 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-02-06 15:07:08 -0800 |
| commit | 13f075e7af30425227cb1323980397d513de76a2 (patch) | |
| tree | 2a2adf005e9ef8897134eefae27833cb96735797 /riscv/processor.cc | |
| parent | 431813d8e27788dd69090c9f6810d06b803891a6 (diff) | |
| download | riscv-isa-sim-13f075e7af30425227cb1323980397d513de76a2.zip riscv-isa-sim-13f075e7af30425227cb1323980397d513de76a2.tar.gz riscv-isa-sim-13f075e7af30425227cb1323980397d513de76a2.tar.bz2 | |
Make JVT CSR definition account for dynamically disabling Zcmt
No functional change yet.
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index d6bc170..f8e8a08 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -508,7 +508,7 @@ void state_t::reset(processor_t* const proc, reg_t max_isa) } } - if (proc->extension_enabled_const(EXT_ZCMT)) + if (proc->extension_enabled(EXT_ZCMT)) csrmap[CSR_JVT] = jvt = std::make_shared<jvt_csr_t>(proc, CSR_JVT, 0); serialized = false; |