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author | Tim Newsome <tim@sifive.com> | 2017-02-06 19:17:23 -0800 |
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committer | Tim Newsome <tim@sifive.com> | 2017-02-06 19:17:23 -0800 |
commit | 4695be7cea868b34082787d5728c35577d0c05d1 (patch) | |
tree | b9d730b3955e924e0b198ccc6c7d5014d06817f9 /riscv/jtag_dtm.h | |
parent | 9be157042081e894e6c12dc96449cf865469bcfe (diff) | |
download | riscv-isa-sim-4695be7cea868b34082787d5728c35577d0c05d1.zip riscv-isa-sim-4695be7cea868b34082787d5728c35577d0c05d1.tar.gz riscv-isa-sim-4695be7cea868b34082787d5728c35577d0c05d1.tar.bz2 |
Refactor remote bitbang code.
Diffstat (limited to 'riscv/jtag_dtm.h')
-rw-r--r-- | riscv/jtag_dtm.h | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/riscv/jtag_dtm.h b/riscv/jtag_dtm.h new file mode 100644 index 0000000..e425c8e --- /dev/null +++ b/riscv/jtag_dtm.h @@ -0,0 +1,81 @@ +#ifndef JTAG_DTM_H +#define JTAG_DTM_H + +#include <stdint.h> + +typedef enum { + TEST_LOGIC_RESET, + RUN_TEST_IDLE, + SELECT_DR_SCAN, + CAPTURE_DR, + SHIFT_DR, + EXIT1_DR, + PAUSE_DR, + EXIT2_DR, + UPDATE_DR, + SELECT_IR_SCAN, + CAPTURE_IR, + SHIFT_IR, + EXIT1_IR, + PAUSE_IR, + EXIT2_IR, + UPDATE_IR +} jtag_state_t; + +class jtag_dtm_t +{ + static const unsigned idcode_ir = 1; + static const unsigned idcode_dr = 0xdeadbeef; + static const unsigned dtmcontrol_ir = 0x10; + + public: + jtag_dtm_t() : + dtmcontrol( + (6 << 4) | // abits + 1 // version + ), + state(TEST_LOGIC_RESET) {} + + void reset() { + state = TEST_LOGIC_RESET; + } + + void set_pins(bool tck, bool tms, bool tdi); + + bool tdo() const { return _tdo; } + + private: + bool _tck, _tms, _tdi, _tdo; + uint32_t ir; + const unsigned ir_length = 5; + uint64_t dr; + unsigned dr_length; + + uint32_t dtmcontrol; + + jtag_state_t state; + + void capture_dr(); + void update_dr(); + + const jtag_state_t next[16][2] = { + /* TEST_LOGIC_RESET */ { RUN_TEST_IDLE, TEST_LOGIC_RESET }, + /* RUN_TEST_IDLE */ { RUN_TEST_IDLE, SELECT_DR_SCAN }, + /* SELECT_DR_SCAN */ { CAPTURE_DR, SELECT_IR_SCAN }, + /* CAPTURE_DR */ { SHIFT_DR, EXIT1_DR }, + /* SHIFT_DR */ { SHIFT_DR, EXIT1_DR }, + /* EXIT1_DR */ { PAUSE_DR, UPDATE_DR }, + /* PAUSE_DR */ { PAUSE_DR, EXIT2_DR }, + /* EXIT2_DR */ { SHIFT_DR, UPDATE_DR }, + /* UPDATE_DR */ { RUN_TEST_IDLE, SELECT_DR_SCAN }, + /* SELECT_IR_SCAN */ { CAPTURE_IR, TEST_LOGIC_RESET }, + /* CAPTURE_IR */ { SHIFT_IR, EXIT1_IR }, + /* SHIFT_IR */ { SHIFT_IR, EXIT1_IR }, + /* EXIT1_IR */ { PAUSE_IR, UPDATE_IR }, + /* PAUSE_IR */ { PAUSE_IR, EXIT2_IR }, + /* EXIT2_IR */ { SHIFT_IR, UPDATE_IR }, + /* UPDATE_IR */ { RUN_TEST_IDLE, SELECT_DR_SCAN } + }; +}; + +#endif |