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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-14 22:36:39 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-05-29 09:01:21 +0800 |
| commit | fecdad2b62cbc4a6baa51d301f0a49d89b81d675 (patch) | |
| tree | 8199d54d7547a317dbccce3248e9bd0f3735c3cb /riscv/isa_parser.h | |
| parent | afe3987685f11058b28988ac9d7e484368246937 (diff) | |
| download | riscv-isa-sim-fecdad2b62cbc4a6baa51d301f0a49d89b81d675.zip riscv-isa-sim-fecdad2b62cbc4a6baa51d301f0a49d89b81d675.tar.gz riscv-isa-sim-fecdad2b62cbc4a6baa51d301f0a49d89b81d675.tar.bz2 | |
Add isa string support for Zfbfmin/Zvfbfmin/Zvfbfwma
Diffstat (limited to 'riscv/isa_parser.h')
| -rw-r--r-- | riscv/isa_parser.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index 9effd16..04859b6 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -49,6 +49,7 @@ typedef enum { EXT_SVINVAL, EXT_ZDINX, EXT_ZFA, + EXT_ZFBFMIN, EXT_ZFINX, EXT_ZHINX, EXT_ZHINXMIN, @@ -57,6 +58,8 @@ typedef enum { EXT_ZICNTR, EXT_ZICOND, EXT_ZIHPM, + EXT_ZVFBFMIN, + EXT_ZVFBFWMA, EXT_XZBP, EXT_XZBS, EXT_XZBE, |