Implement zany immediates

32 files changed, 32 insertions, 32 deletions

diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index 88881e5..d6994ba 100644
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1 +1 @@
-RD = sext_xprlen(RS1 + SIMM);
+RD = sext_xprlen(RS1 + insn.i_imm());
diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h
index 23ae278..a0608ed 100644
--- a/riscv/insns/addiw.h
+++ b/riscv/insns/addiw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(SIMM + RS1);
+RD = sext32(insn.i_imm() + RS1);
diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index 5caea16..713692e 100644
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-RD = SIMM & RS1;
+RD = insn.i_imm() & RS1;
diff --git a/riscv/insns/auipc.h b/riscv/insns/auipc.h
index 48480cd..1c75a40 100644
--- a/riscv/insns/auipc.h
+++ b/riscv/insns/auipc.h
@@ -1 +1 @@
-RD = sext_xprlen(sext32(BIGIMM << IMM_BITS) + pc);
+RD = sext_xprlen(insn.u_imm() + pc);
diff --git a/riscv/insns/clearpcr.h b/riscv/insns/clearpcr.h
index 56c3584..33e0c31 100644
--- a/riscv/insns/clearpcr.h
+++ b/riscv/insns/clearpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->set_pcr(insn.rtype.rs1, p->get_pcr(insn.rtype.rs1) & ~SIMM);
+RD = p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) & ~insn.i_imm());
diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h
index 2704a4d..54d4a77 100644
--- a/riscv/insns/fld.h
+++ b/riscv/insns/fld.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = MMU.load_int64(ITYPE_EADDR);
+FRD = MMU.load_int64(RS1 + insn.i_imm());
diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index afab636..1559ecc 100644
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,2 +1,2 @@
 require_fp;
-FRD = MMU.load_int32(ITYPE_EADDR);
+FRD = MMU.load_int32(RS1 + insn.i_imm());
diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index 0e1c38a..fe90a6b 100644
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,2 +1,2 @@
 require_fp;
-MMU.store_uint64(BTYPE_EADDR, FRS2);
+MMU.store_uint64(RS1 + insn.s_imm(), FRS2);
diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index c921123..85c8091 100644
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,2 +1,2 @@
 require_fp;
-MMU.store_uint32(BTYPE_EADDR, FRS2);
+MMU.store_uint32(RS1 + insn.s_imm(), FRS2);
diff --git a/riscv/insns/jalr.h b/riscv/insns/jalr.h
index 6f17ab1..fa6d7f1 100644
--- a/riscv/insns/jalr.h
+++ b/riscv/insns/jalr.h
@@ -1,3 +1,3 @@
 reg_t temp = RS1;
 RD = npc;
-set_pc((temp + SIMM) & ~1);
+set_pc((temp + insn.i_imm()) & ~1);
diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index 56a5f32..36acd7b 100644
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-RD = MMU.load_int8(ITYPE_EADDR);
+RD = MMU.load_int8(RS1 + insn.i_imm());
diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index 66621c0..f1e9472 100644
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-RD = MMU.load_uint8(ITYPE_EADDR);
+RD = MMU.load_uint8(RS1 + insn.i_imm());
diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index f214294..e57daac 100644
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = MMU.load_int64(ITYPE_EADDR);
+RD = MMU.load_int64(RS1 + insn.i_imm());
diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
index fea2a8e..b158ada 100644
--- a/riscv/insns/lh.h
+++ b/riscv/insns/lh.h
@@ -1 +1 @@
-RD = MMU.load_int16(ITYPE_EADDR);
+RD = MMU.load_int16(RS1 + insn.i_imm());
diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index 71c21be..842a752 100644
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-RD = MMU.load_uint16(ITYPE_EADDR);
+RD = MMU.load_uint16(RS1 + insn.i_imm());
diff --git a/riscv/insns/lui.h b/riscv/insns/lui.h
index 6af2a2a..8dce543 100644
--- a/riscv/insns/lui.h
+++ b/riscv/insns/lui.h
@@ -1 +1 @@
-RD = sext32(BIGIMM << IMM_BITS);
+RD = insn.u_imm();
diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 77f735e..1b4ea35 100644
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-RD = MMU.load_int32(ITYPE_EADDR);
+RD = MMU.load_int32(RS1 + insn.i_imm());
diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index e731178..6c4ad76 100644
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = MMU.load_uint32(ITYPE_EADDR);
+RD = MMU.load_uint32(RS1 + insn.i_imm());
diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index 0f23426..f711931 100644
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->get_pcr(insn.rtype.rs1);
+RD = p->get_pcr(insn.rs1());
diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index 770dfd5..2d4121f 100644
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->set_pcr(insn.rtype.rs1, RS2);
+RD = p->set_pcr(insn.rs1(), RS2);
diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h
index 9561b97..695a56b 100644
--- a/riscv/insns/ori.h
+++ b/riscv/insns/ori.h
@@ -1 +1 @@
-RD = SIMM | RS1;
+RD = insn.i_imm() | RS1;
diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h
index db4d523..8729c2d 100644
--- a/riscv/insns/sb.h
+++ b/riscv/insns/sb.h
@@ -1 +1 @@
-MMU.store_uint8(BTYPE_EADDR, RS2);
+MMU.store_uint8(RS1 + insn.s_imm(), RS2);
diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
index 24c0de9..9364d87 100644
--- a/riscv/insns/sd.h
+++ b/riscv/insns/sd.h
@@ -1,2 +1,2 @@
 require_xpr64;
-MMU.store_uint64(BTYPE_EADDR, RS2);
+MMU.store_uint64(RS1 + insn.s_imm(), RS2);
diff --git a/riscv/insns/setpcr.h b/riscv/insns/setpcr.h
index 4a25d80..2876670 100644
--- a/riscv/insns/setpcr.h
+++ b/riscv/insns/setpcr.h
@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->set_pcr(insn.rtype.rs1, p->get_pcr(insn.rtype.rs1) | SIMM);
+RD = p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) | insn.i_imm());
diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h
index 69234dc..22aa3a8 100644
--- a/riscv/insns/sh.h
+++ b/riscv/insns/sh.h
@@ -1 +1 @@
-MMU.store_uint16(BTYPE_EADDR, RS2);
+MMU.store_uint16(RS1 + insn.s_imm(), RS2);
diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h
index 1f6e50d..8ef4ae7 100644
--- a/riscv/insns/slliw.h
+++ b/riscv/insns/slliw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(RS1 << SHAMTW);
+RD = sext32(RS1 << SHAMT);
diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h
index 1dcd892..51873f3 100644
--- a/riscv/insns/slti.h
+++ b/riscv/insns/slti.h
@@ -1 +1 @@
-RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(SIMM));
+RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(insn.i_imm()));
diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index 45e579b..924fc92 100644
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-RD = cmp_trunc(RS1) < cmp_trunc(SIMM);
+RD = cmp_trunc(RS1) < cmp_trunc(insn.i_imm());
diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
index 4c56730..f43b3fb 100644
--- a/riscv/insns/sraiw.h
+++ b/riscv/insns/sraiw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(int32_t(RS1) >> SHAMTW);
+RD = sext32(int32_t(RS1) >> SHAMT);
diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h
index c400507..2ee1be0 100644
--- a/riscv/insns/srliw.h
+++ b/riscv/insns/srliw.h
@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32((uint32_t)RS1 >> SHAMTW);
+RD = sext32((uint32_t)RS1 >> SHAMT);
diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h
index 81ca71d..aa5ead3 100644
--- a/riscv/insns/sw.h
+++ b/riscv/insns/sw.h
@@ -1 +1 @@
-MMU.store_uint32(BTYPE_EADDR, RS2);
+MMU.store_uint32(RS1 + insn.s_imm(), RS2);
diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h
index 5852aac..4eba233 100644
--- a/riscv/insns/xori.h
+++ b/riscv/insns/xori.h
@@ -1 +1 @@
-RD = SIMM ^ RS1;
+RD = insn.i_imm() ^ RS1;