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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-15 07:57:27 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-15 07:57:27 +0800 |
| commit | b82d97a011315c9f0332c6dcd691f54ca1327d9e (patch) | |
| tree | d93dab15b9577faff8064c04887deee4ecc06b5c /riscv/insns | |
| parent | 887d02e42124ddc86476dfdf4aad4be8ba7f0aef (diff) | |
| download | riscv-isa-sim-b82d97a011315c9f0332c6dcd691f54ca1327d9e.zip riscv-isa-sim-b82d97a011315c9f0332c6dcd691f54ca1327d9e.tar.gz riscv-isa-sim-b82d97a011315c9f0332c6dcd691f54ca1327d9e.tar.bz2 | |
Remove unused parameter for macro in v_ext_macro.h
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/vfncvt_f_f_w.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vfncvt_f_x_w.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vfncvt_f_xu_w.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vfncvt_rod_f_f_w.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vfwcvt_f_f_v.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vfwcvt_rtz_x_f_v.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vfwcvt_rtz_xu_f_v.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vfwcvt_x_f_v.h | 2 | ||||
| -rw-r--r-- | riscv/insns/vfwcvt_xu_f_v.h | 2 |
9 files changed, 0 insertions, 18 deletions
diff --git a/riscv/insns/vfncvt_f_f_w.h b/riscv/insns/vfncvt_f_f_w.h index 40b1051..12bd5a6 100644 --- a/riscv/insns/vfncvt_f_f_w.h +++ b/riscv/insns/vfncvt_f_f_w.h @@ -1,9 +1,7 @@ // vfncvt.f.f.v vd, vs2, vm VI_VFP_NCVT_FP_TO_FP( - {;}, // BODY16 { vd = f32_to_f16(vs2); }, // BODY32 { vd = f64_to_f32(vs2); }, // BODY64 - {;}, // CHECK16 { require_extension(EXT_ZVFHMIN); }, // CHECK32 { require_extension('D'); } // CHECK64 ) diff --git a/riscv/insns/vfncvt_f_x_w.h b/riscv/insns/vfncvt_f_x_w.h index f05ce6b..d5a7b91 100644 --- a/riscv/insns/vfncvt_f_x_w.h +++ b/riscv/insns/vfncvt_f_x_w.h @@ -1,9 +1,7 @@ // vfncvt.f.x.v vd, vs2, vm VI_VFP_NCVT_INT_TO_FP( - {;}, // BODY16 { vd = i32_to_f16(vs2); }, // BODY32 { vd = i64_to_f32(vs2); }, // BODY64 - {;}, // CHECK16 { require_extension(EXT_ZVFH); }, // CHECK32 { require_extension('F'); }, // CHECK64 int // sign diff --git a/riscv/insns/vfncvt_f_xu_w.h b/riscv/insns/vfncvt_f_xu_w.h index 0b9a4d3..71aaf68 100644 --- a/riscv/insns/vfncvt_f_xu_w.h +++ b/riscv/insns/vfncvt_f_xu_w.h @@ -1,9 +1,7 @@ // vfncvt.f.xu.v vd, vs2, vm VI_VFP_NCVT_INT_TO_FP( - {;}, // BODY16 { vd = ui32_to_f16(vs2); }, // BODY32 { vd = ui64_to_f32(vs2); }, // BODY64 - {;}, // CHECK16 { require_extension(EXT_ZVFH); }, // CHECK32 { require_extension('F'); }, // CHECK64 uint // sign diff --git a/riscv/insns/vfncvt_rod_f_f_w.h b/riscv/insns/vfncvt_rod_f_f_w.h index dfba6f4..b36b761 100644 --- a/riscv/insns/vfncvt_rod_f_f_w.h +++ b/riscv/insns/vfncvt_rod_f_f_w.h @@ -1,6 +1,5 @@ // vfncvt.rod.f.f.v vd, vs2, vm VI_VFP_NCVT_FP_TO_FP( - {;}, // BODY16 { // BODY32 softfloat_roundingMode = softfloat_round_odd; vd = f32_to_f16(vs2); @@ -9,7 +8,6 @@ VI_VFP_NCVT_FP_TO_FP( softfloat_roundingMode = softfloat_round_odd; vd = f64_to_f32(vs2); }, - {;}, // CHECK16 { require_extension(EXT_ZVFH); }, // CHECK32 { require_extension('F'); } // CHECK64 ) diff --git a/riscv/insns/vfwcvt_f_f_v.h b/riscv/insns/vfwcvt_f_f_v.h index 9f88c75..111a231 100644 --- a/riscv/insns/vfwcvt_f_f_v.h +++ b/riscv/insns/vfwcvt_f_f_v.h @@ -1,9 +1,7 @@ // vfwcvt.f.f.v vd, vs2, vm VI_VFP_WCVT_FP_TO_FP( - {;}, // BODY8 { vd = f16_to_f32(vs2); }, // BODY16 { vd = f32_to_f64(vs2); }, // BODY32 - {;}, // CHECK8 { require_extension(EXT_ZVFHMIN); }, // CHECK16 { require_extension('D'); } // CHECK32 ) diff --git a/riscv/insns/vfwcvt_rtz_x_f_v.h b/riscv/insns/vfwcvt_rtz_x_f_v.h index f37fc6f..9caf617 100644 --- a/riscv/insns/vfwcvt_rtz_x_f_v.h +++ b/riscv/insns/vfwcvt_rtz_x_f_v.h @@ -1,9 +1,7 @@ // vfwcvt.rtz.x.f.v vd, vs2, vm VI_VFP_WCVT_FP_TO_INT( - {;}, // BODY8 { vd = f16_to_i32(vs2, softfloat_round_minMag, true); }, // BODY16 { vd = f32_to_i64(vs2, softfloat_round_minMag, true); }, // BODY32 - {;}, // CHECK8 { require_extension(EXT_ZVFH); }, // CHECK16 { require_extension('F'); }, // CHECK32 int // sign diff --git a/riscv/insns/vfwcvt_rtz_xu_f_v.h b/riscv/insns/vfwcvt_rtz_xu_f_v.h index 6293dab..a25d847 100644 --- a/riscv/insns/vfwcvt_rtz_xu_f_v.h +++ b/riscv/insns/vfwcvt_rtz_xu_f_v.h @@ -1,9 +1,7 @@ // vfwcvt.rtz,xu.f.v vd, vs2, vm VI_VFP_WCVT_FP_TO_INT( - {;}, // BODY8 { vd = f16_to_ui32(vs2, softfloat_round_minMag, true); }, // BODY16 { vd = f32_to_ui64(vs2, softfloat_round_minMag, true); }, // BODY32 - {;}, // CHECK8 { require_extension(EXT_ZVFH); }, // CHECK16 { require_extension('F'); }, // CHECK32 uint // sign diff --git a/riscv/insns/vfwcvt_x_f_v.h b/riscv/insns/vfwcvt_x_f_v.h index 2dc3763..2d536ad 100644 --- a/riscv/insns/vfwcvt_x_f_v.h +++ b/riscv/insns/vfwcvt_x_f_v.h @@ -1,9 +1,7 @@ // vfwcvt.x.f.v vd, vs2, vm VI_VFP_WCVT_FP_TO_INT( - {;}, // BODY8 { vd = f16_to_i32(vs2, softfloat_roundingMode, true); }, // BODY16 { vd = f32_to_i64(vs2, softfloat_roundingMode, true); }, // BODY32 - {;}, // CHECK8 { require_extension(EXT_ZVFH); }, // CHECK16 { require_extension('F'); }, // CHECK32 int // sign diff --git a/riscv/insns/vfwcvt_xu_f_v.h b/riscv/insns/vfwcvt_xu_f_v.h index aeb02e4..37201f5 100644 --- a/riscv/insns/vfwcvt_xu_f_v.h +++ b/riscv/insns/vfwcvt_xu_f_v.h @@ -1,9 +1,7 @@ // vfwcvt.xu.f.v vd, vs2, vm VI_VFP_WCVT_FP_TO_INT( - {;}, // BODY8 { vd = f16_to_ui32(vs2, softfloat_roundingMode, true); }, // BODY16 { vd = f32_to_ui64(vs2, softfloat_roundingMode, true); }, // BODY32 - {;}, // CHECK8 { require_extension(EXT_ZVFH); }, // CHECK16 { require_extension('F'); }, // CHECK32 uint // sign |