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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2022-02-20 22:42:52 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2022-02-23 19:13:20 -0800 |
| commit | a498c47a73aff56345d45844fe637c6edfdfdb11 (patch) | |
| tree | 07086abb1eeb31b4838cfaa5734e0a420dd3830d /riscv/insns | |
| parent | 53a3002e8cdbf94016d36c6071945bd663e826d5 (diff) | |
| download | riscv-isa-sim-a498c47a73aff56345d45844fe637c6edfdfdb11.zip riscv-isa-sim-a498c47a73aff56345d45844fe637c6edfdfdb11.tar.gz riscv-isa-sim-a498c47a73aff56345d45844fe637c6edfdfdb11.tar.bz2 | |
csr: mstatus.sxl and mstatus.uxl are zero in rv32
dont' set mstatus.sxl and mstatus.uxl in rv32 mode
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns')
0 files changed, 0 insertions, 0 deletions