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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-16 10:42:58 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-21 14:12:53 +0800 |
| commit | 383dbd3822042cdeb00c11597838bc1078271a22 (patch) | |
| tree | fd50787169694a6bb3a7bd8e1556d61eba793a50 /riscv/insns | |
| parent | 04154f2b305c222674c8cecf692b1b63edc8c6cb (diff) | |
| download | riscv-isa-sim-383dbd3822042cdeb00c11597838bc1078271a22.zip riscv-isa-sim-383dbd3822042cdeb00c11597838bc1078271a22.tar.gz riscv-isa-sim-383dbd3822042cdeb00c11597838bc1078271a22.tar.bz2 | |
Add r1s != r2s check for cm.mvsa01
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/cm_mvsa01.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/insns/cm_mvsa01.h b/riscv/insns/cm_mvsa01.h index 949d2f8..7288fbd 100644 --- a/riscv/insns/cm_mvsa01.h +++ b/riscv/insns/cm_mvsa01.h @@ -2,5 +2,6 @@ require_extension(EXT_ZCMP); if (p->extension_enabled('E')) { require((insn.rvc_r1sc() < 2) && (insn.rvc_r2sc() < 2)); } +require(insn.rvc_r1sc() != insn.rvc_r2sc()); WRITE_REG(RVC_R1S, READ_REG(X_A0)); WRITE_REG(RVC_R2S, READ_REG(X_A1)); |