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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-06-28 10:38:40 +0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-11-17 16:40:00 -0800 |
| commit | 087626c280571b13e5ee51a3a7603c8bbd96916a (patch) | |
| tree | 5c630c7ff388d119bf9ef68221a38b9679f824aa /riscv/insns | |
| parent | 1160ea7f1b1026884bef3b8ac2caf613c8e9a475 (diff) | |
| download | riscv-isa-sim-087626c280571b13e5ee51a3a7603c8bbd96916a.zip riscv-isa-sim-087626c280571b13e5ee51a3a7603c8bbd96916a.tar.gz riscv-isa-sim-087626c280571b13e5ee51a3a7603c8bbd96916a.tar.bz2 | |
add support for zcmt
add suport for jvt: Table entries follow the current data endianness
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/cm_jalt.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/riscv/insns/cm_jalt.h b/riscv/insns/cm_jalt.h new file mode 100644 index 0000000..163adaa --- /dev/null +++ b/riscv/insns/cm_jalt.h @@ -0,0 +1,23 @@ +require_extension(EXT_ZCMT); +STATE.jvt->verify_permissions(insn, false); +reg_t jvt = STATE.jvt->read(); +uint8_t mode = get_field(jvt, JVT_MODE); +reg_t base = get_field(jvt, JVT_BASE); +reg_t index = insn.rvc_index(); +reg_t target; +switch (mode) { +case 0: // jump table mode + if (xlen == 32) + target = MMU.fetch_jump_table<int32_t>(base + (index << 2)); + else // xlen = 64 + target = MMU.fetch_jump_table<int64_t>(base + (index << 3)); + + if (index >= 32) // cm.jalt + WRITE_REG(1, npc); + + set_pc(target & ~reg_t(1)); + break; +default: + require(0); + break; +} |