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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-16 10:42:08 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-21 14:12:53 +0800 |
| commit | 04154f2b305c222674c8cecf692b1b63edc8c6cb (patch) | |
| tree | 4fbda5e7782df92304b5ffc35c44ef64bb93731e /riscv/insns | |
| parent | 72df59bec2b2eaa3438a41b33df608571048d6ed (diff) | |
| download | riscv-isa-sim-04154f2b305c222674c8cecf692b1b63edc8c6cb.zip riscv-isa-sim-04154f2b305c222674c8cecf692b1b63edc8c6cb.tar.gz riscv-isa-sim-04154f2b305c222674c8cecf692b1b63edc8c6cb.tar.bz2 | |
Update fields name for sreg1/sreg2
Diffstat (limited to 'riscv/insns')
| -rw-r--r-- | riscv/insns/cm_mva01s.h | 6 | ||||
| -rw-r--r-- | riscv/insns/cm_mvsa01.h | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/riscv/insns/cm_mva01s.h b/riscv/insns/cm_mva01s.h index c8d4284..6212a8e 100644 --- a/riscv/insns/cm_mva01s.h +++ b/riscv/insns/cm_mva01s.h @@ -1,6 +1,6 @@ require_extension(EXT_ZCMP); if (p->extension_enabled('E')) { - require((insn.rvc_sreg1() < 2) && (insn.rvc_sreg2() < 2)); + require((insn.rvc_r1sc() < 2) && (insn.rvc_r2sc() < 2)); } -WRITE_REG(X_A0, READ_REG(RVC_SREG1)); -WRITE_REG(X_A1, READ_REG(RVC_SREG2)); +WRITE_REG(X_A0, READ_REG(RVC_R1S)); +WRITE_REG(X_A1, READ_REG(RVC_R2S)); diff --git a/riscv/insns/cm_mvsa01.h b/riscv/insns/cm_mvsa01.h index 1822bc1..949d2f8 100644 --- a/riscv/insns/cm_mvsa01.h +++ b/riscv/insns/cm_mvsa01.h @@ -1,6 +1,6 @@ require_extension(EXT_ZCMP); if (p->extension_enabled('E')) { - require((insn.rvc_sreg1() < 2) && (insn.rvc_sreg2() < 2)); + require((insn.rvc_r1sc() < 2) && (insn.rvc_r2sc() < 2)); } -WRITE_REG(RVC_SREG1, READ_REG(X_A0)); -WRITE_REG(RVC_SREG2, READ_REG(X_A1)); +WRITE_REG(RVC_R1S, READ_REG(X_A0)); +WRITE_REG(RVC_R2S, READ_REG(X_A1)); |