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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-14 01:30:08 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-02-18 09:19:44 -0800 |
| commit | eeba38241d4bc9cca1f3b3acfd2564baa51edf76 (patch) | |
| tree | 8ffd8fc3a4f107368093127a3818ae1422acbfd5 /riscv/insns/vssrl_vi.h | |
| parent | 6b143cd0a244c5ad38bdbfe88495647496e62dd5 (diff) | |
| download | riscv-isa-sim-eeba38241d4bc9cca1f3b3acfd2564baa51edf76.zip riscv-isa-sim-eeba38241d4bc9cca1f3b3acfd2564baa51edf76.tar.gz riscv-isa-sim-eeba38241d4bc9cca1f3b3acfd2564baa51edf76.tar.bz2 | |
rvv: make variable name match its meaning
zimm5 for unsigned and zero-extended
simm5 for signed and signed-extended
It is unsigned arithmetics
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vssrl_vi.h')
| -rw-r--r-- | riscv/insns/vssrl_vi.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vssrl_vi.h b/riscv/insns/vssrl_vi.h index 55e085d..d125164 100644 --- a/riscv/insns/vssrl_vi.h +++ b/riscv/insns/vssrl_vi.h @@ -2,7 +2,7 @@ VRM xrm = P.VU.get_vround_mode(); VI_VI_ULOOP ({ - int sh = simm5 & (sew - 1) & 0x1f; + int sh = zimm5 & (sew - 1) & 0x1f; uint128_t val = vs2; INT_ROUNDING(val, xrm, sh); |