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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-01-13 09:09:24 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-01-24 08:36:37 -0800 |
| commit | 331017800023159b54ad7a5e3f701d6ac8d7b6a8 (patch) | |
| tree | c3bc8866ae50afd82955e04bb0f8f13cf6408901 /riscv/insns/vssrl_vi.h | |
| parent | 6e3d1537a4a6668cdbe2f78e651754c98a2fec24 (diff) | |
| download | riscv-isa-sim-331017800023159b54ad7a5e3f701d6ac8d7b6a8.zip riscv-isa-sim-331017800023159b54ad7a5e3f701d6ac8d7b6a8.tar.gz riscv-isa-sim-331017800023159b54ad7a5e3f701d6ac8d7b6a8.tar.bz2 | |
rvv: fix corner case when input are 1's and shift amount is maximum
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vssrl_vi.h')
| -rw-r--r-- | riscv/insns/vssrl_vi.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vssrl_vi.h b/riscv/insns/vssrl_vi.h index bf554ca..55e085d 100644 --- a/riscv/insns/vssrl_vi.h +++ b/riscv/insns/vssrl_vi.h @@ -3,7 +3,7 @@ VRM xrm = P.VU.get_vround_mode(); VI_VI_ULOOP ({ int sh = simm5 & (sew - 1) & 0x1f; - uint64_t val = vs2; + uint128_t val = vs2; INT_ROUNDING(val, xrm, sh); vd = val >> sh; |