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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-15 03:39:00 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-29 21:38:43 -0700 |
| commit | effb92a5ecca543e27bb0ae3d7c42eee34d4ddf4 (patch) | |
| tree | 744bd308e8c7dd38ea31c5203c4fffa78483b648 /riscv/insns/vs8r_v.h | |
| parent | 3075210b4948fb1b0a6772384c6e2ea103d75511 (diff) | |
| download | riscv-isa-sim-effb92a5ecca543e27bb0ae3d7c42eee34d4ddf4.zip riscv-isa-sim-effb92a5ecca543e27bb0ae3d7c42eee34d4ddf4.tar.gz riscv-isa-sim-effb92a5ecca543e27bb0ae3d7c42eee34d4ddf4.tar.bz2 | |
rvv: add new whole reg load/store instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vs8r_v.h')
| -rw-r--r-- | riscv/insns/vs8r_v.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/insns/vs8r_v.h b/riscv/insns/vs8r_v.h new file mode 100644 index 0000000..1ad2575 --- /dev/null +++ b/riscv/insns/vs8r_v.h @@ -0,0 +1,2 @@ +// vs8r.v vs3, (rs1) +VI_ST_WHOLE |