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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-01 00:45:20 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-04 09:50:05 -0700 |
commit | b216e03dd1c10d17693053a1eb83a20fff3242ea (patch) | |
tree | e143204aa5fa83b6bac321026e10f791444d39a2 /riscv/insns/vfadd_vv.h | |
parent | d78999f0c7c44317b0c3fc2d34217418b5dbe086 (diff) | |
download | riscv-isa-sim-b216e03dd1c10d17693053a1eb83a20fff3242ea.zip riscv-isa-sim-b216e03dd1c10d17693053a1eb83a20fff3242ea.tar.gz riscv-isa-sim-b216e03dd1c10d17693053a1eb83a20fff3242ea.tar.bz2 |
rvv: fp16: support .vv instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vfadd_vv.h')
-rw-r--r-- | riscv/insns/vfadd_vv.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/insns/vfadd_vv.h b/riscv/insns/vfadd_vv.h index b333a8a..ce94921 100644 --- a/riscv/insns/vfadd_vv.h +++ b/riscv/insns/vfadd_vv.h @@ -1,6 +1,9 @@ // vfadd.vv vd, vs2, vs1 VI_VFP_VV_LOOP ({ + vd = f16_add(vs1, vs2); +}, +{ vd = f32_add(vs1, vs2); }, { |