Split Xbitmanip into its proposed component extensions (#918)

Before this patch, spike just had an "Xbitmanip" extension which
covered everything in the proposed bitmanip extension that hadn't been
ratified. The problem is that if you want to model (or verify) a
processor that targetted just some of the proposed bitmanip extension,
you couldn't configure Spike to do that.

For example, the lowRISC Ibex processor has several different
configurations. The "balanced" configuration targetted Zba, Zbb, Zbs,
Zbf and Zbt of the 0.92 spec. With the Zba, Zbb and Zbs ratified,
we'll now be able to use an ISA string like

    rv32imc_Zba_Zbb_Zbs_XZbf_XZbt

and Spike will correctly fail to decode instructions like 'bcompress',
which would have been decoded with Xbitmanip.

This patch adds a new custom extension name for each part of the
extension that wasn't fully ratified. These have an 'X' prefix so, for
example, the bit permutation instructions that were proposed as Zbp
can be found under XZbp.

Specifying "Xbitmanip" gets all of these extensions, so its behaviour
should be unchanged.

Note that the slo(i) / sro(i) instructions have been moved from the
proposed Zbb to XZbp. This matches a comment in the Change History
section of v0.93 of the bitmanip spec: it seems that the authors
forgot to also move them in Table 2.1 (which gives the lists of
instructions for each extension). This change won't break anything
that currently exists, but it took quite a while to figure out what
was going on so I thought I'd leave a breadcrumb trail for the next
engineer!

The bulk of the patch is just defining some more entries in the
isa_extension_t enum and rewriting each of the instructions to depend
on the relevant entry. This is mostly a straight textual replacement
but it's slightly more complicated for things like the "pack"
instruction that are defined by several different proposed extensions.

1 files changed, 1 insertions, 1 deletions

diff --git a/riscv/insns/sroiw.h b/riscv/insns/sroiw.h
index 32b4ef9..8348070 100644
--- a/riscv/insns/sroiw.h
+++ b/riscv/insns/sroiw.h
@@ -1,3 +1,3 @@
 require_rv64;
-require_extension(EXT_XBITMANIP);
+require_extension(EXT_XZBP);
 WRITE_RD(sext32(~((~(uint32_t)RS1) >> SHAMT)));