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| author | marcfedorow <mark.fedorov@cloudbear.ru> | 2021-07-08 23:09:06 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-08 13:09:06 -0700 |
| commit | 21f4b59d3ae16ebf14752c2dfd580646f7612152 (patch) | |
| tree | 17860bc1e1865ed71e34717e8049fea475cac147 /riscv/insns/srai32_u.h | |
| parent | db6f5795270c922d52041fd016261982687dd145 (diff) | |
| download | riscv-isa-sim-21f4b59d3ae16ebf14752c2dfd580646f7612152.zip riscv-isa-sim-21f4b59d3ae16ebf14752c2dfd580646f7612152.tar.gz riscv-isa-sim-21f4b59d3ae16ebf14752c2dfd580646f7612152.tar.bz2 | |
Fixed range issues on sr<al>[i]32.u insns (see #695) (#740)
Diffstat (limited to 'riscv/insns/srai32_u.h')
| -rw-r--r-- | riscv/insns/srai32_u.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/srai32_u.h b/riscv/insns/srai32_u.h index 5c7b06c..5c4330d 100644 --- a/riscv/insns/srai32_u.h +++ b/riscv/insns/srai32_u.h @@ -1,7 +1,7 @@ require_rv64; P_I_LOOP(32, 5, { if (imm5u > 0) - pd = ((ps1 >> (imm5u - 1)) + 1) >> 1; + pd = (((uint64_t)(ps1 >> (imm5u - 1))) + 1) >> 1; else pd = ps1; })
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