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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-09-27 00:15:35 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-09-27 00:15:35 -0700 |
| commit | c8a8c07ec296ce36dc04f2448faf48fe1c502a2d (patch) | |
| tree | a497ddda532182cc10aa2f82a555e0d3ab4d220c /riscv/insns/srai.h | |
| parent | 6554cdd3fb42bc3833a1888f87dfc67c9099500c (diff) | |
| download | riscv-isa-sim-c8a8c07ec296ce36dc04f2448faf48fe1c502a2d.zip riscv-isa-sim-c8a8c07ec296ce36dc04f2448faf48fe1c502a2d.tar.gz riscv-isa-sim-c8a8c07ec296ce36dc04f2448faf48fe1c502a2d.tar.bz2 | |
Use WRITE_RD/WRITE_FRD macros to write registers
Diffstat (limited to 'riscv/insns/srai.h')
| -rw-r--r-- | riscv/insns/srai.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h index 7360d5f..7fdbdf3 100644 --- a/riscv/insns/srai.h +++ b/riscv/insns/srai.h @@ -1,8 +1,8 @@ if(xpr64) - RD = sreg_t(RS1) >> SHAMT; + WRITE_RD(sreg_t(RS1) >> SHAMT); else { if(SHAMT & 0x20) throw trap_illegal_instruction(); - RD = sext32(int32_t(RS1) >> SHAMT); + WRITE_RD(sext32(int32_t(RS1) >> SHAMT)); } |