Priv virtual memory updates (#750)

* Priv virtual memory updates

* Priv 1.12 requires page faults when the address translation process
reaches a PTE with any reserved bit set

* Svpbmt uses two PTE bits, but otherwise has no effect on Spike (since
Spike is sequentially consistent and does not model PMAs)

* Add Svinval instructions

Even though I updated riscv-opcodes separately, I merged the new
defines into riscv/encoding.h manually, because riscv-opcodes seems
to be a step ahead of riscv-isa-sim for a few vector opcodes, causing
conflicts when regenerating encoding.h...

If that gets fixed, and encoding.h gets regenerated automatically, I can
remove it from this PR to avoid conflicts.

* Svinval: use #include rather than copying code

..for the Svinval functions that are implemented in ways that just
mimic SFENCE/HFENCE instructions

Thanks to @aswaterman for the suggestion

1 files changed, 2 insertions, 0 deletions

diff --git a/riscv/insns/sfence_w_inval.h b/riscv/insns/sfence_w_inval.h
new file mode 100644
index 0000000..10d8dd6
--- /dev/null
+++ b/riscv/insns/sfence_w_inval.h
@@ -0,0 +1,2 @@
+require_extension('S');
+require_impl(IMPL_MMU);